JPH01204484A - Superconductor electronic device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to superconductor electronic devices, and more particularly to pressure-gated transistors.

[Conventional technology]

Among conventional transistors, a Schottky barrier field effect transistor is, for example, an n-type G field effect transistor, as shown in FIG.
A gate electrode 102 is provided on the surface of the a As conductive layer 101 and is in Schottky contact with the Ga As. It is controlled by the thickness of the depletion layer 105 formed on the n-type GaAs surface. Sincerely, male world-bound form Josephson (Jos)
The three-terminal element (ephson) provides a small input by coupling the magnetic field created by the current flowing through the wiring to the Josephson element.Furthermore, the Josephson type field effect transistor is as shown in Figure 8. A voltage is applied to the weak coupling part 109 of the degenerate region formed between the superconductor-semiconductor junction of the weakly coupled Josephson element to form a depletion layer, and a depletion layer flows between the source electrode 106 and the drain electrode 108 of the superconductor. It controls the number of superconducting electrons.

[Problem to be solved by the invention]

Among the above-mentioned FC bag transistors, the Schottky barrier field effect transistor has a problem in that a mutual conductance gm of only about 100 m5 can be obtained because the channel resistance is large. In addition, the magnetic field coupling type Josephson 3-terminal element has a magnetic flux Φo (='2..07XIO"5Wb)
2, so it is difficult to achieve high integration with such devices.Moreover, Josephson field effect transistors have high device resistance due to semiconductor bonding junctions, and There is a problem that hysteresis occurs in the fiI-V characteristics.

An object of the present invention is to provide a new superconductor electronic device that has a large mutual conductance and can be highly integrated.

[Tth means to solve the problem]

The superconductor electronic device of the present invention includes a superconductor crystal layer of a predetermined shape that is adhered to the surface of an insulating substrate and has a crystal plane exhibiting superconductivity two-dimensionally in a direction parallel to the surface; A pressure gate including a companion piezoelectric element is provided across the pressure gate, and a source electrode and a drain/electrode are formed of a pair of conductive films deposited on the superconducting crystal layer and sandwiching the pressure gate. It is something.

[For production]

Ceramic crystals with pseudoperovskite structure and KINiF4 type structure, which are known as ceramic superconductors, are Y
-i (La, yb.

Tm, Er, Ho, Dy, Tb, Gd, Eu, Sm) and alkaline earth metals (Ba, Ca, Sr, etc.) and 2
L n -A-Cu consisting of (Cu, Ag) of valence and 0
(A'g) is an oxide that exhibits superconductivity such that its electrical resistance becomes zero at low temperatures.

Y51. 'Ba52. A superconductor consisting of Cu53,054, for example YBa2cu306.69, belongs to the orthorhombic system as shown in Figure 4, and has a lattice constant (a = 3.8845
^, b: 3.8293A, C=xx, er93M), it is long in the C-axis direction and has a structure in which the Cu-0 bond chain 55 expands infinitely in the ab plane perpendicular to the C-axis. . The planes of this Cu-0 bond chain 55 are laminated in layers in the C-axis direction, and the superconductivity of the crystal is caused by the hybridization of the Cu 3d orbit and the 0 2p orbit of the Cu-0 bond chain. It is said that strongly bound t-electrons are generated at the t-th point where t-electrons form a high-density conduction band 7-luminium surface. Therefore, the superconductivity of the crystal occurs only in the a-b plane perpendicular to the C-axis, that is, only in the Cu-0 bond chain plane, and there is a two-dimensionality of conduction in which there is a slight leakage in the C-axis direction. There are characteristics to show. In a superconducting crystal that exhibits such two-dimensional superconductivity, when pressure is applied in the direction perpendicular to the C axis, the Cu-0 bond distance in the ab plane becomes small, and as a result, the superconducting dislocation temperature Tc increases. It is known that electrical resistance decreases.

The principle of this invention is source and drain! The channel conductance of the superconductor crystal between the poles is controlled by applying pressure to the crystal and changing the state density distribution of the heptagonal aluminum plane of the Cu-0 bond chain. Whereas applying pressure perpendicular to the C-axis increases the channel conductance in the a-b plane.

If pressure is applied in the C-axis direction, the channel conductance will conversely decrease. Therefore, in the present invention, a pressure gate such as a piezoelectric element is arranged so as to completely cross the surface of a superconducting crystal layer that becomes a channel, and a bias input is given to the piezoelectric element to drive the pressure gate to perform electric/positive conversion. Pressure is applied in the C-axis direction of the superconductor crystal layer, and by applying this pressure, the channel conductance between the source and drain electrodes is controlled, making it a normally-on transistor. By arranging the pressure gate so as to completely traverse the surface of the superconducting crystal layer serving as the channel, the superconducting current flowing through the channel can be completely pinched off by the pressure gate.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a chip showing a first embodiment of the present invention.

In this example, (10
A rectangle (1 cm
xO, 1 cm) superconductor crystal layer (YBazCu30s
, s9 crystal layer 11) and a piezoelectric element (PZT) provided on and across the YBazcu 30ass crystal layer 11.
(membrane 31 and a pair of comb-shaped electrodes 41, 42)
t-containing pressure gate and the aforementioned pressure gate) 7-inch te YB
A source electrode 21 and a drain electrode 22 made of a pair of conductive films deposited on the crystal layer 11
It should be called a pressure gate field effect transistor.

Next, the manufacturing method of this example will be explained.

FIGS. 2(a) and 2(b) are cross-sectional views of chips arranged in the order of steps to explain the manufacturing method of the first embodiment. First, as shown in FIG. of the board 1o (
sputtering on the surface (100)
g) Since it was deposited by the method, it was heat treated to a thickness of 1mm.
A YBazCuaOa6s crystal layer 11 gold having a width of -1 cm and a length of 5 mm is provided. At this time, YBazCusOe69I
! ! i! The r-crystalline layer 11 has its C-axis in a direction perpendicular to the MgO substrate 10 .

Next, as shown in FIG. 2(b), YBazCu30s
, the crystal film 11 including a plane parallel to the C axis of the s9 crystal layer 1
A source electrode fi21 and a drain electrode 22 are provided by depositing K Au f on both ends of the electrode. Next, as shown in Figure 1, −zYBa2C is sandwiched between the source electrode 21 and the drain electrode 22.
A 1 μm thick P was used as a pressure gate to completely traverse the surface of the u30as9 crystal layer 11 and to be displaced in the direction perpendicular to the crystal film, that is, in the C-axis direction, by applying a voltage.
A piezoelectric element is provided on the ZT (= solid solution of Zr-Ti-Pb) 31 and the pZT:n and is detached from the l pair of comb-shaped electrodes 41 and 42 (made of Au) for inputting the t-gate signal. . When this embodiment is cooled to about 80K and a maximum of 1 cm of gate signal input is applied to the comb-shaped electrode ff141.42, the comb-shaped electrode 41.42 depends on the magnitude of the input voltage.
PZT film 31f YBa zcu 306. s
9 expands in the direction perpendicular to the crystal layer 11 surface, resulting in P
By applying pressure to the superconductor crystal layer immediately below the ZT film 31, the interstitial space of this crystal film can be changed. As is well known, when pressure is applied in the C-axis direction, the lattice spacing in the ab-plane where Cu-0 bond chains are present increases9, and the superconducting current decreases accordingly. In the case of this embodiment, as shown in Fig. 3,
When inputting Vg==lV to the pressure gate, the superconducting current generator da
5OA when inputting 0■ was controlled by OA. If the pressure gate width or channel width 't is 1 cm, the transconductance corresponds to 5000 mS/mm.

FIG. 5 is a sectional view of a chip showing a second embodiment.

In this embodiment, a sapphire substrate 60 is used as an insulating substrate,
As a superconductor crystal layer (La-Ca)zAgo4 crystal r
Except for the use of ftf and t, this is the same as in the first embodiment.

Next, the manufacturing method of the second embodiment will be explained. As shown in FIG. 6 fa), the (0
112) A 1 mm thick (La-Ca)2Ag04 crystal layer 61' is formed on the surface and heat-treated. At this time, (La
-Ca), Ago4 belongs to the orthorhombic system, and (La-
The C axis of the Ca)1Ag04 crystal layer 61 is the sapphire substrate 6
It becomes perpendicular to 0.

Next, as shown in FIG. 6(b), (La − Ca )
*A on both ends of the AgO4 crystal layer 61 including the plane parallel to the C axis.
A source electrode 21 and a drain electrode 22 are provided by depositing u.

Next, as shown in FIG. 5, a voltage is applied to the surface of the *(La-Ca)I Ag04 crystal layer 61 sandwiched between the source and drain electrodes, thereby applying pressure such that the superconductor film is displaced in the C-axis direction. A PZT 31 with a thickness of 1 μm is used as a gate, and a comb-shaped electrode c1, 42 for a gate signal is provided on the PZT.
' is provided.

The pressure gate type transistor of the present invention obtained in this way was cooled to about 30K and applied to the comb-shaped electrodes 41 and 42 at a maximum of 1V.
When the gate signal input vg is given, the superconducting current between the source and drain electrodes is suppressed from 3OA when OV is large input to QA. When the channel width is t-1 cm, the mutual conductance corresponds to 3000 m5A plane.

In the above embodiments, YBa2C is used as the electromotive conductor crystal.
L1301L69. and (La-Ca)2Ag04
In the example below, PZT is used as an example of the pressure gate material.
Even if other superconductors such as -Q type or other piezoelectric crystals such as fcLiTaOs or LiNb0a are used, the idea of the present invention will not be impaired. The substrates that can be used are not limited to MgO and sapphire, but also
It goes without saying that the present invention is applicable to anything that can grow a superconductor film, such as a crystal.

〔Effect of the invention〕

As explained above, the present invention applies a gate signal of about 1 V to a pressure gate provided on a plane parallel to the plane showing superconductivity of a superconductor crystal layer.

It controls the superconducting current between the source and drain of the superconductor crystal by changing the state density distribution of the 7-luminium plane of the bonded chain of the superconductor crystal, and has an extremely large mutual co/ductance of 3 to 5 x 103 m5/mm. A superconductor electronic device having high noise can be obtained. Furthermore, in many conventional transistors, the characteristics depend on the cleanliness of the boundary between the gate electrode and the crystal film and are extremely sensitive to the surface, but the present invention modulates the characteristics by applying mechanical displacement using a pressure gate. Therefore, it also has the effect that the surface properties are insensitive to the surface and stable.

In addition, if a piezoelectric element is used as a pressure gate, the size of the transistor can be reduced, and high integration is also easy.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a chip showing a first embodiment of the present invention;
Figures 2 (al) and (b) are cross-sectional views of the ninth chip arranged in the order of steps to explain the manufacturing method of the first embodiment, and Figure 3 is the ninth signal waveform to explain the operation of the embodiment. 4 is a structural model diagram of YBa2Cu30s, s9 crystal, FIG. 5 is a cross-sectional view of a chip showing the second embodiment, and FIG. 6 (al,
(bl is a cross-sectional view of a T chip arranged in the order of the ninth process to explain the manufacturing method of the second embodiment, FIG. 7 is a cross-sectional view of a chip showing a Schottky barrier field effect transistor gold, and FIG.
The figure is a cross-sectional view of a chip showing a Jose7 type field effect transistor. 10 ・--・-pgo substrate, 11-----・-YBa
2CusO6,69 crystal layer, 21...source electrode, 22...dray/electrode, 31...
PZTl[,41,42...Comb-shaped electrode for gate signal input, 51...Yl 52...
・Ba, 53...Cu, 54...0.
55...Cu-0 bond chain, 60...Sapphire substrate, 61...(La-Ca)IAg
O4 crystal layer, 101 ---n-type trench conductor layer, 102...
...Gate electrode, 106... Superconductor source electrode, 107... Superconductor gate electrode, 10
8... Superconductor drain electrode, 105, 109...
... Depletion layer of weak coupling part, 110 ... Semiconductor substrate. Agent Patent Attorney Uchihara Oto No. 1 Mata-etsu 2nd Circle No. 3 Kasino 4 Kasumi No. 5 Figure 6 Kasao q Figure No. 8 Kasumi

Claims (1)

[Claims] a superconductor crystal layer of a predetermined shape that is deposited on the surface of an insulating substrate and has a crystal plane exhibiting superconductivity two-dimensionally in a direction parallel to the surface; and a superconductor crystal layer provided on the superconductor crystal layer across the layer. A superconductor electronic device comprising: a pressure gate including a piezoelectric element; and a source electrode and a drain electrode made of a pair of conductive films deposited on the superconductor crystal layer with the pressure gate in between.