JPH0120459B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor system having a plurality of processors each connected to a common system bus.

[Prior Art] Conventionally, in various electronic devices, multiple processors such as microcomputers are connected to a system bus, and resources such as large-capacity memory connected to the system bus are mutually sent and received to perform advanced and complex processing. There is a system using a multiprocessor system that has made this possible.

However, in conventional multiprocessor systems, the right to use the system bus is managed by a bus arbiter in order to prevent simultaneous access to the system bus from each processor. In addition to the complexity, complicated conditions must be determined before permission to use the system bus is determined, resulting in a reduction in overall throughput.

Note that conventionally, as in the computer system described in Japanese Patent Application Laid-open No. 48-87741, two sets of buffer memories are provided in a peripheral device, and the buffer memories are alternately connected to the computer and the peripheral device to send data. There is a system in which data requests from a peripheral control device to a computer are averaged in response to data requests from peripheral devices.
- Like the data processing method described in Publication No. 115142, data from the pre-processing section is alternately written to the memory according to the first-in-first-out method, and read out to the post-processing section, thereby reducing the variation in data processing time. There is a data transfer device that prevents data from dropping or slipping based on 2-side buffer memory. A register means is provided for storing the leading part of the signal, and data subsequent to the input signal is written into one of the buffer memories.
In some devices, the data stored in the registration means is read out before reading out the written data, so that the data can be completely read out when changing the buffer memory surface.

However, the above-mentioned computer system of JP-A-48-87741, data processing method of JP-A-55-115142, and data transfer device of JP-A-55-134442 do not support data transmission and reception in a multiprocessor system. If one attempts to utilize the above-mentioned conventional examples in a multiprocessor system, a circuit for bus arbitration such as a bus arbiter will be required, resulting in the above-mentioned drawbacks.
Furthermore, each of the above conventional examples is for unidirectional data transmission and reception, and has the disadvantage that it is not suitable for bidirectional data transmission and reception.

[Purpose of the invention]

The present invention was devised in view of the above-mentioned drawbacks, and is capable of bidirectional data transmission and reception between processors without reducing throughput, and has a simple circuit configuration that eliminates the need for a circuit for bus arbitration such as a bus arbiter. The purpose is to provide an inexpensive multiprocessor system.

[Structure of the invention]

In the present invention, one of the processors is a master processor, the remaining processors are slave processors,
A memory having two memory blocks is provided corresponding to each slave processor, and the memory blocks of each memory are selectively switched to the master processor side and the slave processor side under the control of the master processor. Data is sent and received between the master processor and each slave processor.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention, in which a master processor 2, a large capacity memory 3, and a plurality of slave processors 4-1 to 4-N are connected to a system bus 1. . In this case, the slave processors 4-1 to 4-N have an input register 41 and an output register 42, 2 for sending and receiving commands between the slave CPU 40 and the master processor 2, as shown in FIG.
A random access memory (RAM) 43 having two memory blocks A and B is provided.

In such a configuration, for example, a case where the slave processor 4-1 receives data from an external device (not shown) and transfers this data to the master processor 2 will be explained. Setusa 4-1
A command for instructing the input register 41 to input data from an external device is set. As a result, the slave CPU 40 executes the data input operation from the external device, and sequentially stores the input data in the B memory block of the RAM 43. While repeating this data input operation, when the write address to the B memory block reaches the final address, the slave CPU
40 writes a command representing this to the output register 42 and interrupts the master processor 2.

Then, the master processor 2, which was executing other processing during this time, detects that the B memory block of the RAM 43 in the slave processor 4-1 has become full due to an interrupt from the slave processor 4-1. , sends a switching command to the slave processor 4-1 to connect the B memory block to the system bus 1 instead of the A memory block. This memory block switching command is sent to the slave via the input register 41.
given to the CPU 40. This allows the slave
The CPU 40 gives a switching signal to the RAM 43, and
A B memory block is coupled to the system bus 1 instead of the memory block.

As a result, the B memory block can now be accessed from the master processor 2, and the data stored in the B memory block can be accessed by the master processor 2.
The data is read into the master processor 2 by the read operation and written into the large capacity memory 3.

Next, we will explain the case where the data stored in the large capacity memory 3 is output to an external device connected to the slave processor 4-N, for example. In this case, first, the data stored in the large capacity memory 3 is It is written to memory block A of RAM 43 in processor 4-N.

Next, the master processor 2 sends a switching command to the slave processors 4-N to connect the B memory block to the system bus 1 instead of the A memory block. As a result, the B memory block is coupled to the system bus 1, and the A memory block storing transfer data from the master processor 2 is coupled to the bus line of the slave processor 40.

Therefore, in order to output the data stored in the A memory block to the external device, a command is set from the master processor 2 to the input register 41 of the slave processor 4-N to instruct the data output operation to the external device. As a result, the slave CPU 40 sequentially reads data from the A memory block and executes a data output operation to an external device.

When the read address of the A memory block reaches the final address while repeating such data output operation, the slave CPU 40 sends a command indicating this to the output register 42.
and interrupts the master processor 2.

Then, the master processor 2, which was executing other processing during this time, detects that memory block A of the RAM 43 in the slave processor 4-N has become empty due to an interrupt from the slave processor 4-1. , sends a switching command to the slave processor 4-N to connect the A memory block to the system bus 1 instead of the B memory block. This memory block switching command is sent to the slave CPU via the input register 41.
given to 40. This allows the slave CPU
40 provides a switching signal to the RAM 43 to couple the A memory block to the system bus 1 instead of the B memory block.

In this way, data transmission and reception between the master processor 2 and each slave processor 4-1 to 4-N is performed.
This is done by alternately switching the memory blocks of the RAM 43. Therefore, after switching the memory blocks, the master processor 2 and each slave CPU 40 can independently use the A memory block or the B memory block and execute their respective processes independently. As a result, a decrease in throughput can be prevented. Furthermore, since it is not necessary to make complicated conditional judgments when using the system bus 1, a circuit such as a bus arbiter is not required, the configuration can be simplified, and the overall throughput can be improved. Also, a master processor 2 for transmitting and receiving data.
Since communication between the CPU and each slave processor 4-1 to 4-N is based on interrupt operations, there are advantages such as a small overhead.

〔Effect of the invention〕

As explained above, in the present invention, an interrupt is issued to the master processor depending on the state of data storage in the memory block, that is, whether the write address to the memory block is the final address, and the master processor is activated based on the interrupt. Since the slave processor switches memory blocks for data storage in response to switching instructions, bidirectional data transmission and reception between each processor is possible without reducing throughput, and bus arbitration circuits such as a bus arbiter are not required. Therefore, since the circuit configuration can be simplified, manufacturing costs can be reduced.

[Brief explanation of drawings]

FIG. 1 is an overall block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing an example of the configuration of a slave processor. 1...System bus, 2...Master processor, 3...Large capacity memory, 4-1 to 4-N...Slave processor, 40...Slave CPU, 4
1...Input register, 42...Output register, 43...Random access memory.

Claims (1)

[Scope of Claims] 1. A master processor, at least one slave processor, two memory blocks provided corresponding to the slave processor and sequentially storing data, the master processor, the slave processor and In a multiprocessor system having a system bus connecting memory blocks and transmitting and receiving data between the master processor and the slave processor, the slave processor is configured to control the state of data storage in the memory block. means for detecting, means for interrupting the master processor according to the detection result, and means for switching memory blocks for data storage in response to a switching instruction of the master processor based on the interrupt, A multiprocessor system characterized in that bidirectional data transmission and reception is performed between the master processor and the slave processor.