JPH04357548A - multiprocessor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor that uses a plurality of processors each having a built-in data memory and is used for image data processing and the like.

0002

2. Description of the Related Art FIG. 10 shows the concept of the configuration of a conventional multiprocessor. FIG. 10(a) shows a central processing unit (ICPU) 602 and a data memory (IDM) inside the chip.
A multiprocessor is shown in which a processor 601 having a processor 603 and another processor 604 mutually access a shared memory 606 via a shared memory bus 605 . When transferring data between processors in this multiprocessor, for example, the central processing unit (ICPU) 602 transfers data to the data memory (IDM) 603.
data is transferred to the shared memory 606, and the processor 604 reads the data from the shared memory 606.

FIG. 10(b) also shows a central processing unit (ICPU) 612 and a data memory (IDM) inside the chip.
613 and DMA (direct memory ac
A processor 611 having a cess) circuit 614 and another processor 615 are connected to a shared memory bus 61.
This is a multiprocessor that mutually accesses the shared memory 617 via 6. Data transfer between processors in this multiprocessor is performed by the processor 61.
Since the processor 611 has a DMA circuit 614 inside it, this DMA circuit 614 is used for data input/output to/from the data memory (IDM) 613 performed by the processor 611 .

That is, FIG. 11 is a conceptual diagram of the conventional processor 701 (611) shown in FIG. 10(b). This processor 701 is a central processing unit (I) equipped with various arithmetic units, registers, sequencers, instruction analysis circuits, etc.
A data memory (IDM) 704 (613) and a DMA device 705 are connected to the memory bus 703 of the CPU) 702 (612).
(614) is connected. The memory bus 703 can also access memory devices outside the chip via an external memory port 706. When the amount of data is large, input/output of data to/from a data memory (IDM) 704 in this processor 701 is normally performed by a DMA device 705.
This is done using

[0005] In this data transfer method, a central processing unit (ICPU) 702 sets address information and data amount information in advance for the DMA device 705, and when a startup command is issued, the DMA device 705 becomes independent. and IDM
Data transfer to 704 begins. When the amount of data has been transferred, the DMA device 705 transfers the data to the central processing unit (
702 to notify the end of the transfer.

[0006]

[Problem to be Solved by the Invention] However, in the above-described multiprocessor, when data generated within each processor is transferred between processors, it must be written to a shared memory outside the processor and then read. Therefore, it takes time to transfer data to this shared memory, and since a shared memory bus must be constructed, there is a problem that the peripheral circuitry becomes large.

The present invention of claim 1 (hereinafter referred to as the first invention) takes into consideration the problems of conventional multiprocessors, eliminates the time required to transfer data to a shared memory, and also realizes a reduction in hardware. The purpose is to provide a multiprocessor that can

Another object of the present invention (hereinafter referred to as the second invention) is to realize a multiprocessor that can access the internal memory of the processor from the outside as its own memory.

[0009] The present invention as claimed in claim 3 (hereinafter referred to as the third invention) is an application program that processes a huge amount of data, when the data can be divided and processed in parallel. The purpose of the present invention is to provide a multiprocessor that requires less hardware by reducing the time required for data transfer and eliminating the need for shared memory.

[0010]Furthermore, the present invention as claimed in claim 4 (hereinafter referred to as the fourth invention) is an application program for information processing data, when the information processing can be performed in pipeline parallel processing in terms of time. The present invention aims to provide a multiprocessor that requires less hardware by reducing the time required for data transfer between processors and by eliminating the need for a shared memory.

[0011]

[Means for Solving the Problems] In the first invention, the central processing unit (ICPU) usually occupies the access right to the data memory (IDM), and the central processing unit (ICPU)
relinquish the right to access the data memory (IDM) by its own command, or another central processing unit (ECPU) sends a signal to the central processing unit (ICPU) to forcibly acquire the right to access the data memory (IDM). This is a multiprocessor in which access rights to the data memory (IDM) are delegated to other central processing units (ECPUs).

[0012] The second invention is a central processing unit (ICPU)
data memory (IDM) from and external to the processor.
), and a control means for controlling the selection means. Usually, the control means is a central processing unit (ICP).
U) controls the selection means so that it is in the master mode that occupies the access right to the data memory (IDM), and a forced access right acquisition signal is added to a specific terminal of the processor from outside the processor, or a central processing Device (IC
Depending on whether an access right transfer command possessed by the processor (PU) is executed, the control means controls the selection means to enter a slave mode in which the access right to the data memory (IDM) is delegated to the outside of the processor. from,
By adding a master mode transition signal to a specific terminal of the central processing unit (ICPU), the central processing unit (ICPU)
ICPU) is a processor whose state transitions to master mode.

[0013] In a multiprocessor using a plurality of processors, when data is transferred between processors, a specific processor constituting the multiprocessor is designated as a processor (master processor) in charge of data transfer, and a transfer partner is By putting the processor (slave processor) in the slave mode according to claim 2, and arranging the data memory built into the slave processor in the address space of the master processor, communication between the master processor and the slave processor, and between the slave processors is achieved. Data transfer between the two processors is realized by moving data in the master processor's own address space, and after the data transfer is completed, the master processor transitions the slave processor to the master mode of claim 2, and the slave processor receives the transferred data. A multiprocessor that executes processing on stored data.

[0014] A fourth invention is a multiprocessor using a plurality of processors according to the second invention, in which a second
When the data memory in the third processor is arranged in the address space of the second processor and the data memory in the third processor is arranged in the address space of the second processor, and data transfer between the first and second processors is performed, The master processor operates in the master mode of claim 2, and the second processor to be transferred is the slave processor that operates in the slave mode of claim 2, and the data transfer between the first processor and the second processor is as follows: This is realized by the first processor moving data in its own address space, and after the data transfer is completed, the master processor transitions the slave processor to the master mode as defined in claim 2, and the slave processor transfers the transferred data. When performing processing on the second invention and transferring data between the second and third processors, the second processor is operated in master mode as the master processor of the second invention, and the third processor, which is the transfer partner, is operated in master mode. The processor is operated in slave mode as the slave processor of the second invention, and data transfer between the second processor and the third processor is realized by the second processor moving data in its own address space. After the data transfer is completed, the second processor causes the third processor to enter the master mode, and the third processor is a multiprocessor that executes processing on the transferred data.

[0015]

[Operation] In the first invention, by delegating access rights to the data memory inside the processor, it can be treated as the external processor's own memory, thereby eliminating the time required to transfer data to the shared memory and reducing the amount of hardware required. .

[0016] In the second invention, a circuit is realized which allows the memory inside the processor to be accessed from the outside as its own memory.

[0017] In the third invention, in an application that processes a huge amount of data, when the data can be divided and processed in parallel, the time required for data transfer between the processors can be reduced, and the shared memory is not required. By eliminating the need for hardware.

[0018] In the fourth invention, in an application that processes data, when a specific process can be processed in parallel in terms of pipeline processing, the time required for data transfer between the processors is reduced. , and eliminates the need for shared memory.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings.

FIG. 1 shows the concept of the configuration of a multiprocessor according to the first invention. This multiprocessor consists of a processor 101 which internally includes a central processing unit (ICPU) 102 and a data memory (IDM) 103 consisting of a large capacity DRAM, SRAM, etc. of several kilowatts or more, and a processor (ECPU) 104. , an external memory 105, and a memory bus 106 connecting them. Both an external memory 105 and the data memory (IDM) 103 can be placed in the memory space of the processor (ECPU) 104, as will be described later.

In this multiprocessor, access rights to the data memory (IDM) 103 are granted not only to the central processing unit (ICPU) 102 but also to the processor (ECPU) 1.
It also has 04. and typically a central processing unit (IC)
PU) 102 has exclusive access rights to the data memory (IDM) 103, and the data memory (IDM) 1
Processor (ECPU) 10 with access rights to 03
4 is realized by executing an access right transfer instruction output from the central processing unit (ICPU) 102, or by the processor (ECPU) 104 sending a forced access right acquisition signal to the processor 101. It has become. I will discuss this in detail later.

Note that the state in which the central processing unit (ICPU) 102 has exclusive access rights to the data memory (IDM) 103 is indicated using a terminal or the like external to the processor. and processor (ECPU) 104
Access to the data memory (IDM) 103 by
This is done by determining the state of the terminals mentioned above, as will be described in detail later.

Note that while the central processing unit (ICPU) 102 is delegating the access right to the data memory (IDM) 103, the central processing unit (ICPU) 102 uses resources other than the data memory (IDM) 103. It is permissible to execute the command. 2, 3, and 4 are flowcharts showing control of access to the IDM 103 by a multiprocessor in the first invention.

In TYPE-1 of FIG. 2, the ICPU 102 has acquired access rights to the IDM 103, and the
102 executes its own access right transfer command, then checks the external terminal of the processor 101 (terminal indicating the access right status of the IDM 103), and if the access right is delegated, the ECPU 104 accesses the IDM 103. It is.

TYPE-2 and TYPE-3 in FIGS. 3 and 4
This is a scene in which the ECPU 104 accesses the IDM 103 while the ICPU 102 is acquiring access rights to the IDM 103.

[0026] TYPE-2 waits for the ECPU 104 to access the IDM 103 under hardware or software control until the ICPU 102 delegates the access right, and then the ICPU 102 executes the access right transfer instruction and transfers the access right. This is a method of accessing the IDM 103 after abandoning it. Control by hardware or software is performed via an external terminal (I) of the processor 101.
(terminal indicating the access right status of the DM 103).

[0027] In TYPE-3, the ECPU 104
This is a control for acquiring access rights by forcibly delegating the access rights to U102 and accessing the IDM 103. This control is performed by the ECPU sending a forced access right acquisition signal to the processor 101.
The ICPU 102 in the IDM 103 temporarily relinquishes the access right to the IDM 103 and notifies the ECPU 104 of the status through an external terminal of the processor 101 (a terminal indicating the status of the access right of the IDM 103). After confirming the state of the external terminal, the ECPU 104 accesses the IDM 103, then relinquishes the temporarily acquired access right to the IDM 103, and the ICPU 102 reacquires the access right to the IDM 103 to continue processing.

In the above multiprocessor,
Data transfer between processors is performed using data memory (IDM)
This can be achieved by simply delegating access rights to 103. In other words, data processed by the central processing unit (ICPU) 102 is transferred to the processor (ECPU) 104.
The central processing unit (ICPU) 102 can simply execute an instruction to transfer access rights to the processor 104, and the processor (ECPU) 104 can transfer information processing to the central processing unit (ICPU) 102. In the case of transferring the transferred data, a forced access right acquisition signal is sent to the processor 101, and if the access right transfer is established, the transfer of the access right is realized.

Note that the built-in memory on the processor 104 side can also be accessed from the processor 101 side in the same way as the data memory (IDM) 103, so that both the processors 101 and 104 can be made equal.

FIG. 5 shows the configuration of a processor according to the second invention. The processor 201 embodies the processor 101 of the first invention, and includes a central processing unit (ICPU) 202 including various arithmetic units, registers, a sequencer, an instruction analysis circuit, etc., and a data memory (IDM) 203.
, a selection circuit 204 that switches between address lines and data lines;
and a control circuit 205 that controls delegation of access rights to the data memory (IDM) 203. The rest is the same as the configuration in FIG. 1 (not shown).

[0031] In such a multiprocessor,
The central processing unit (ICPU) 202 has a data memory (I
DM) 203 is implemented to transfer the access right to the outside of the processor (ISLV instruction), and the central processing unit (ICPU) 202 occupies the access right to the data memory (IDM) 203. (master mode), its central processing unit (ICPU
) 202 outputs an access rights delegation instruction (ISLV instruction) for the data memory (IDM) 203, which is input to the control circuit 205, which in turn causes the selection circuit 204 to transfer the signal from outside the processor 201 to the data memory. (IDM) 203. That is, 204a and 204b related to addresses, 204c related to write and read information, and 20 related to data.
Switch 4d to external. Further, when the switching is completed, a notification that the access right has been delegated to the outside of the processor 201 is sent via the terminal ST.

Further, when a forced access right acquisition signal (ESLV/RUN=1) is added from outside the processor 201, the control circuit 205 controls the central processing unit (ICPU) 2.
02, or prohibits access to the data memory (IDM) 203. Thereafter, the control circuit 205 controls the selection circuit 204 as described above to supply a signal from outside the processor 201 to the data memory (IDM) 203 (slave mode). When the switching is completed, the terminal ST indicates that the access right has been transferred to an external party of the processor 201.
Notify via.

Due to these two factors, when the access right is delegated to an external device of the processor 201 (slave mode), if the external processor 104 outputs a master mode transition signal (ESLV/RUN=0). , a control circuit 205 controls a selection circuit 204 to supply a signal from a central processing unit (ICPU) 202 to a data memory 203 (IDM). That is, 204a and 204b related to addresses, 204c related to write and read information, and 204d related to data are connected to the central processing unit (IC).
PU) Switch for 202. When the switching is completed, the access right is transferred to the central processing unit (ICPU) 202, and the return (master mode) is signaled to the terminal ST.
Notify via.

In the slave mode, the external processor 104 accesses the data memory (IDM) 203 in the same way as normal memory access. That is, for the processor 104, the data memory (
IDM) 203 is a memory for a predetermined number. For this purpose, a chip selection signal terminal CS is provided. The upper address is decoded and this chip selection signal terminal C
The decoded signal may be connected to S.

Note that the WE terminal is for reading and writing information.

Furthermore, a plurality of data memories and their control circuits for performing the above-described control may be incorporated.

FIG. 6 shows the configuration of a multiprocessor according to the third invention.

This multiprocessor includes a master processor 301 and two slave processors 302 and 303.
and control circuits 304 and 305 that control the decoding circuit for the upper address of the address bus of the master processor 301 and the access rights to the data memory.

This multiprocessor performs parallel processing using a master processor 301 and two slave processors 302 and 303. The slave processors 302 and 303 are composed of the processors according to the second invention described above, and have built-in data memory, and the data memory can have access rights delegated to the master processor 301 using the control method described above. There is. The data memories built into the slave processors 302 and 303 are each mapped onto the memory space of the master processor 301, as shown in the address space diagram of FIG.

Parallel processing in a multiprocessor as described above is an application that processes a huge amount of input data such as image processing, and when data can be divided and processed in parallel, processing on the divided data is performed by a slave. This is used when the processors 302 and 303 share the task.

Processing operations in parallel processing using this multiprocessor are as follows.

The divided data is sent to the master processor 30.
1 attempts to allocate data to the data memory built into each slave processor 302, 303 using its own DMA device or its own built-in DMA device. Therefore, for example, the master processor 301 sends a forced access right acquisition signal (ESLV/
RUN=1) is sent to slave processors 302 and 303 to set them in slave mode. As a result, the data memories of the slave processors 302 and 303 can be treated as the memories of the master processor 301, so input data can be stored in the data memories of the slave processors 302 and 303 from the beginning. slave processor 3
Once the input data is on the data memory of 02 and 303,
Master processor 301 transmits a master mode transition signal to slave processor 3 via control circuits 304 and 305.
Send to 02,303. Then slave processor 3
02 and 303 recover the access right and execute information processing in parallel on the input data existing on their own data memory. The data obtained by the information processing is stored on the data memory, where the slave processors 302 and 303 execute an access right transfer instruction and
Notify T terminal. The master processor 301 monitors its status (ST terminal) via the control circuits 304 and 305, and if the access right transfer is established (processing is completed), the master processor 301 transfers the status to the slave processor 30.
2. Access the output data stored in the data memory in 303. The application is executed by repeatedly performing such processing. Furthermore, data transfer between slave processors 302 and 303 can also be performed as described above.

FIG. 8 shows the configuration of a multiprocessor according to the fourth invention.

[0044] This multiprocessor includes a processor 50
1 to 503, and control circuits 504 and 505 that perform control over decoding circuits for upper addresses of address buses of processors 501 and 502 and access rights to data memories.

[0045] This multiprocessor includes processor 50
1 to 503 perform parallel processing. Each of the processors 501 to 503 is constituted by a processor according to the second invention and has a built-in data memory. Access rights to the data memory can be delegated to a higher-level processor using the control method described in the second invention. That is, the data memories built in processors 502 and 503 are stored in the upper processor 501, respectively.
, 502. The processor 502 has a data memory and its control circuit, etc.
It is built-in. That is, FIG. 9 shows a configuration diagram when two data memories are built into the processor 101. Two types of control circuits, selectors, and external terminals are prepared for each of the two data memories. There are also two types of access right transfer instructions. One of these memory buses is for access from the upper processor 501,
The other is for accessing the lower processor 503.

[0046] Note that such a function can be realized even by using one data memory.

The operation of parallel processing in the multiprocessor as described above will now be explained.

[0048] In an application that processes data, when a certain specific process can be processed in parallel in a pipeline in terms of time, the divided processing is distributed to each processor, and the output data is sent to the lower processor. It will be sequentially transferred to.

The flow of processing in parallel processing using this multiprocessor is such that divided processing (programs) are placed in each processor in advance, and data transfer and processing between the upper and lower processors is as follows: 2nd above
This can be realized by controlling the upper processor as a master processor and the lower processor as a slave processor in the same way as the method of the invention. For example, the processor 501 obtains access rights to the data memory 502a of the processor 502, transfers data from its own data memory, and the processor 502 transfers the data to its own data memory 502a.
Transfer to 02b. Thereafter, the processor 502 has access rights to the data memory of the processor 503, and transfers data from its own data memory 502b to the data memory of the processor 503, and so on.

[0050]

[Effects of the Invention] As is clear from the above explanation, according to the first invention, by delegating access rights to the data memory inside the processor, it can be treated as the external processor's own memory. It is possible to eliminate transfer time and provide a multiprocessor that reduces hardware.

According to the second invention, the memory inside the processor can be accessed from the outside as a normal memory.

According to the third invention, in an application that processes a huge amount of data, when the data can be divided and processed in parallel, the time required for data transfer between the processors can be reduced, and the shared memory can be By eliminating the need for , it is possible to provide multiprocessors with reduced hardware.

According to the fourth invention, in an application that processes data, when a certain specific process can be processed in parallel in a pipeline in terms of time,
It reduces the time required to transfer data between processors,
Moreover, it is possible to eliminate the need for shared memory.

The above-mentioned present invention exhibits its advantages significantly in the field of image processing where processing of a large amount of data is required.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a multiprocessor according to a first invention.

FIG. 2 is a flow diagram for explaining the operation of the multiprocessor according to the first invention.

FIG. 3 is a flow diagram for explaining the operation of the multiprocessor according to the first invention.

FIG. 4 is a flow diagram for explaining the operation of the multiprocessor according to the first invention.

FIG. 5 is a block diagram of an embodiment of a processor according to the second invention.

FIG. 6 is a block diagram of an embodiment of a multiprocessor according to a third invention.

FIG. 7 is a memory map diagram of a multiprocessor according to a third invention.

FIG. 8 is a block diagram of an embodiment of a multiprocessor according to a fourth invention.

FIG. 9 is a block diagram showing part of the circuit of FIG. 8;

FIG. 10 is a block diagram showing the concept of the configuration of a conventional multiprocessor.

FIG. 11 is a block diagram showing the concept of the conventional processor in FIG. 10;

[Explanation of symbols]

101 Processor 102 Central Processing Unit (ICPU) 103 Data Memory (IDM) 104 External Processor 105 External Memory 201 Processor 203 Data Memory 204 Selection Means 205 Control Means 301 Master Processor 302, 303 Slave Processor 304, 305
control means

Claims (4)

[Claims] [Claim 1] In a multiprocessor that includes a processor with a central processing unit (ICPU) and a data memory (IDM) inside, and another central processing unit (ECPU) outside the processor, the central A processing unit (ICPU) occupies the access right to the data memory (IDM), and the central processing unit (ICPU)
) relinquish access to the data memory (IDM) on its own command, or the other central processing unit (EDM)
By sending a forced access right acquisition signal to the data memory (IDM) to the central processing unit (ICPU), the access right to the data memory (IDM) is granted to the other central processing unit (ECPU). A multiprocessor characterized by being delegated to. 2. In a processor having a built-in central processing unit (ICPU) and a data memory (IDM), there is no charge to the data memory (IDM) from the central processing unit (ICPU) and from outside the processor. It is equipped with a selection means for switching between an address line and a data line to enable access, and a control means for controlling the selection means, and usually the control means is connected to the central processing unit (ICP).
U) controls the selection means so that the processor is in a master mode that occupies the right to access the data memory (IDM), and a forced access right acquisition signal is added to a specific terminal of the processor from outside the processor; , or whether an access right transfer instruction possessed by the central processing unit (ICPU) is executed, the control means is configured to enter a slave mode in which the access right to the data memory (IDM) is transferred to an external party of the processor. A master mode transition signal is added to a specific terminal of the central processing unit (ICPU) from outside the processor, thereby controlling the selection means to
U) is a processor characterized by a state transition to master mode. 3. In a multiprocessor using a plurality of processors, when data is transferred between the processors, a specific processor constituting the multiprocessor is designated as a processor in charge of data transfer (master processor) and serves as a transfer partner. Putting the processor (slave processor) into the slave mode according to claim 2,
By arranging the data memory built in the slave processor in the address space of the master processor, data transfer between the master processor and the slave processors and between the slave processors is performed in the master processor's own address space. After the data transfer is completed, the master processor causes the slave processor to transition to the master mode according to claim 2, and the slave processor executes processing on the transferred data. A multiprocessor featuring 4. A multiprocessor using a plurality of processors according to claim 2, wherein a data memory in a second processor is arranged in an address space of a first processor constituting the multiprocessor; When the data memory in the third processor is arranged in the address space of , and data transfer between the first and second processors is performed, the first processor is set as the master processor operating in the master mode of claim 2, and the data transfer is performed. A second processor as a partner is a slave processor operating in the slave mode of claim 2, and data transfer between the first processor and the second processor is performed by the first processor in its own address space. This is realized by performing data movement, and after the data transfer is completed, the master processor causes the slave processor to transition to the master mode as defined in claim 2, and the slave processor executes processing on the transferred data, When data is transferred between the second and third processors, the second processor is operated in master mode as the master processor of claim 2, and the third processor to be transferred is operated as the slave processor of claim 2. The second processor operates in slave mode, and data transfer between the second processor and the third processor is realized by the second processor moving data in its own address space. 2. The second processor comprises the third processor in claim 2.
A multiprocessor characterized in that the third processor executes processing on transferred data.