JPH0120508B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for detecting signals detected from a recording medium.
The present invention relates to a reference level setting circuit for digital signal detection, which is configured to automatically change a reference level that separates high-level and low-level periods of a detection signal so that an accurate original digital signal is detected.

Recently, audio signals (analog signals)
Convert to PCM signal and optically record to disk,
A digital audio disk for playback has been proposed. In this case, it has been considered to record digital data on a disk using a suitable digital modulation method, such as 8/14 modulation (converting 8-bit data to 14-bit data, called EFM modulation). In order to obtain the original digital signal from the recorded disc in this manner, the high level period and low level period can be determined by comparing the signal picked up by the pickup means with an appropriate reference level. . However, if this standard level is not set accurately,
The obtained (detected) digital signal becomes an inaccurate signal, and the error rate of digital data reproduction increases. It is not preferable to set this reference level uniquely. This is because actual signals obtained from disks vary over time between disks and even within the same disk due to variations in disk write conditions and disk fluctuations during playback.

Therefore, the present invention is configured to automatically change the reference level, so that a digital signal having accurate high level and low level periods can always be detected. Hereinafter, the present invention will be explained in detail based on Examples.

In the currently proposed digital audio disks, digital data is EFM modulated and recorded. With EFM modulation, 8 data bits of data are converted to 14 channel bits of data, but since the number of data that can be expressed with 14 bits is naturally greater than the number of data that can be expressed with 8 bits, 14 Some constraints can be placed on the channel bit data. For example, data of 14 channel bits
When recording in the NRZ system, a restriction can be imposed that the signal inversion interval (high level and low level period) is 3 channel bits or more and 11 channel bits or less. Therefore, in the embodiment described below, the reference level is automatically changed so that the minimum signal inversion interval becomes the interval of three regular channel bits.

Comparator 1 contains the data obtained from the pick-up means.
The EFM signal (Figure 2 a) is input with its DC component cut off by a capacitor 2, and a reference level signal (Figure 2 g), which is normally at 0 level, is also input, so that the reference level The high level and low level periods of the EFM signal a are determined with respect to g, and an EFM digital signal as shown in FIG. 2b is created. The reference level signal g is output from a reference level changing circuit 3 composed of an up/down counter 4 and a D/A converter 5, and the output of the counter 4 is normally 0.
Since the EFM signal a obtained from the pickup means has a distorted waveform, the obtained EFM digital signal b varies depending on the position of the reference level g.

The EFM digital signal b is input to the determination circuit 6 , and the minimum period of high level and low level periods is a period equivalent to regular 3 channel bits (approximately 694 ns).
It is determined whether or not.

The monostable multivibrator 7 and the D-type flip-flop 8 have a low level period of a predetermined period (approximately
694ns) or less, it is determined whether the reference level g is below the appropriate level h. The monostable multivibrator 7 is triggered by the fall of the signal b, and the Q output (FIG. 2c) is at a high level for the predetermined period. Flip-flop 8 is in a reset state when the reset input is at a low level, and reads the data input (signal c) in response to the rising edge of the T input (signal b) when the reset input is at a high level. According to FIG. 2, the low level period of the EFM digital signals b ₁ and b ₂ is less than the predetermined period, and at this time, the Q of the flip-flop 8 is
Judgment pulses d ₁ and d ₂ are obtained from the output. Therefore,
The counter 4 counts up in response to this determination pulse, and the output of the D/A converter 5 increases, pushing the reference level g upward and bringing it closer to the appropriate level h.

The monostable multivibrator 9 and the D-type flip-flop 10 determine whether the reference level g is higher than the appropriate level h by determining whether the high level period is shorter than a predetermined period. (See Figure 3). In this case, a signal obtained by inverting the signal b by the inverter 11 is used. Then, if the reference level g
If G is shifted upward, judgment pulses f ₁ , f ₂ , f ₃ are obtained, the counter 4 counts down, the output of the D/A converter 5 decreases, and the reference level g is pushed downward to reach the appropriate level. Bring it closer to h.

Although the explanation so far has been based on the use of the minimum signal inversion interval, the maximum signal inversion interval (equivalent to 11 channel bits) may also be used. However, if dropout occurs, the maximum signal reversal interval becomes longer, causing an inconvenience, and a shorter monostable period is more accurate in driving a monostable multivibrator that exhibits a regular signal reversal interval. (Even if the same 5% error occurs, the shorter the period, the smaller the error amount).From this point of view, it is more convenient to use the minimum signal inversion interval (3 channel bits).

According to the present invention described above, the minimum or maximum signal inversion interval (high level or low level period)
Since the reference level can be automatically changed so that the value becomes a normal value, an accurate digital signal can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a reference level setting circuit for digital signal detection according to the present invention, and FIGS. 2 and 3 are operational waveform diagrams thereof. 3 is a reference level change circuit, and 6 is a judgment circuit.

Claims (1)

[Claims] 1. In detecting the original digital signal by determining the high level and low level periods of the signal by comparing the signal detected from the recording medium with a reference level, the high level of the signal is determined. and a determination circuit that determines whether the low level period is less than (or more than) the regular minimum (or maximum) period, and a criterion for automatically changing the reference level based on the output of this determination circuit. A reference level setting circuit for digital signal detection, characterized in that a level changing circuit is provided.