JPH0120511B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field of the Invention The present invention relates to a memory configuration system, in particular, a memory configuration system that assigns an address to each bit of a storage element that stores data, and stores data of a predetermined bit length starting from a specified address. This relates to a memory configuration method for access.

(B) Technical Background and Problems In the conventional memory configuration system, one address is assigned to each bit of a plurality of storage elements, for example, 8 bits, as one word. Therefore, if one word of data to be processed is divided into two addresses as shown in Figure 1A, for example data from a bit map display device, special processing is required. Become. First, after reading one word of data at the first address where necessary data exists (FIG. 1B), significant data is shifted to the left end (FIG. 1C). Next, after reading one word of data at an address obtained by adding 1 to the first address (FIG. 1D), significant data is shifted to the right end. and,
Each significant data obtained (Fig. 1 C and E) had to be combined to obtain one word of data (Fig. 1 F). For this reason, many memory accesses are required, and the accessed data must be subjected to a shifting process, which poses a problem in writing or reading data to or from a desired location in a storage element at high speed.

(C) Object and Structure of the Invention The present invention assigns an address to each bit of a storage element that stores data, and accesses data of a predetermined bit length starting from the specified address at once, thereby allowing arbitrary storage of the storage element to be performed. The purpose is to access data at high speed. Therefore, in the memory configuration method of the present invention, in a memory configuration method in which data is written to a storage element at a specified address or data is read from a storage element, an address is attached to a bit correspondence of a storage element that stores data, and an address is assigned to a bit correspondence of the storage element that stores data. It is characterized by having a plurality of memories that can be read and written, and writing data to or reading data from a storage element corresponding to a predetermined bit length starting from a designated address.

(D) Embodiments of the Invention The present invention will be described in detail below with reference to the drawings.

FIG. 2 shows a conceptual diagram of the present invention, FIG. 3 shows the configuration of one embodiment of the invention, FIG. 4 shows details of the address selector shown in FIG. 3, and FIG. FIG. 2 shows a diagram illustrating data access. In the figure, 1 is a memory address register, 2 is a counter, 3 is a select control, 4 is a shift control, 5 is an address selector, 6 is a memory,
7 represents a 2 ⁿ bit rotating shift register.

FIG. 2A shows a conceptual diagram of the present invention, in which an address is assigned to each bit of a memory element. FIG. 2B shows the relationship between addressing and data as shown in FIG. 2A.

In order to read data, for example, if address 2 is specified, the data is a predetermined bit length following the address 2, in this case 4 bits of data, so the data contained in addresses up to address 5 will be read. It is read out as shown in Figure 2B. Similarly, by specifying the address 3 or 8, 4-bit data is read out (FIG. 2B). In addition, when writing, if you specify the address along with the data as shown in Figure 2B, for example address 2, then
Predetermined data, here 4-bit data, is stored from address 2 onward in the figure. By assigning an address to each bit of the memory element in this manner, data located at an arbitrary position in the memory element can be read out at high speed or written to an arbitrary position.

In FIG. 3, there are two types of address signals, a specified upper address signal and an address signal with 1 added to it, and based on the lower address signal corresponding to one word length, one of the two types of upper address signals is After selecting one address signal having significant bit data corresponding to one word and reading out the data at once (Figure 5B), this read data is rotated and shifted (Figure 5C). This is an example of reading out one word of data at high speed. An embodiment of a memory having an address length of (m+n) bits and a data length of ²ⁿ bits according to the present invention will be described below.

In FIG. 3, an (m+n)-bit address signal input from a computer or the like through an address bus is latched into a memory address register (MAR). Among the (m+n) bit address signals latched in MAR, the high-order m bits are output to internal bus A, and a signal which is input to counter 2 and incremented by 1 is output to internal bus B. On the other hand, among the (m+n) bit address signals latched to MAR, the lower n bits are selected by select control 3 and shift control 4.
supply to. The address signal of the lower n bits supplied to the select control 3 is decoded into ²ⁿ signals and supplied to the corresponding address selector 5, respectively. Based on the signal supplied from the select control 3, the address selector 5 supplies one of the address signals from the internal bus A or the internal bus B to the memory 6. Thereby, the memory 6 supplies only significant bit data to the 2 ⁿ bit rotating shift register 7. The shift control 4 supplies pulses corresponding to the number of contents of the supplied address signal of the lower n bits to the 2 ⁿ bit rotation shift register 7, and rotates the significant bit data as shown in FIG. 5C. The data is shifted, arranged into predetermined data, and output to the data bus as ^2n- bit data.

Further, when writing data to the memory, the data may be input to the 2 ⁿ bit rotation shift register 7, and after performing a predetermined rotation, the data may be written to the memory 6.

FIG. 4 shows details of the address selector 5 shown in FIG.
Address selector 5 selects a selection signal for accessing significant bit data based on the nbit signal.
Supplied to the output sending terminal (OUT PUT ENABLE) of mbit bus buffer 5-2 located inside. That is, at input n of select control 3, output Ci is
Ci={0i input 1i>input}. On the other hand, mbit
A selection signal inverted by an inverter is supplied to the bus buffer 5-1. As a result, the address select 5 sends an address signal for accessing significant bit data from the bus A or bus B, respectively.

FIG. 5 shows a diagram explaining the data access shown in FIG. 3.

"1 access" shown in FIG. 5A indicates a data area that is accessed once by the upper address m, and "1 word" indicates a significant data area that is desired to be accessed.

FIG. 5B shows a state in which bit data is read into the 2 ⁿ bit rotating shift register 7 shown in FIG.

FIG. 5C shows a state in which the bit data in FIG. 5B is rotated and shifted to obtain data for one predetermined word. When writing data, see Figure 5C,
By reversing the procedure for reading B and A in this order,
Write to a specified location in memory.

(E) Effects of the Invention As explained above, according to the present invention, an address is attached to each bit of a memory element that stores data,
1 for a series of addresses starting from the specified address
Since data can be written or read with multiple accesses, it is possible to read or write data at any location at high speed. This is particularly effective in bitmap display devices and the like.

[Brief explanation of drawings]

FIG. 1 shows a diagram explaining bit processing using a conventional memory configuration method, FIG. 2A shows a conceptual diagram of the present invention, and FIG. 2B shows the relationship between address designation and data as shown in FIG. 2A. 3 shows the configuration of one embodiment of the present invention, FIG. 4 shows details of the address selector shown in FIG. 3, and FIG. 5 shows a diagram explaining the data access shown in FIG. 3. In the figure, 1 represents a memory address register, 2 a counter, 3 a select control, 4 a shift control, 5 an address selector, 6 a memory, and 7 a 2 ⁿ bit rotating shift register.

Claims (1)

[Claims] 1. In a memory configuration method that writes data to or reads data from a storage element at a specified address, an address is assigned to each bit of the storage element that stores data, and multiple memories that can be read and written to each bit are created. A memory configuration method characterized in that data is written to or read from a storage element corresponding to a predetermined bit length starting from a specified address.