JPH01205355A - Cache memory - Google Patents

Abstract

PURPOSE:To prevent the degradation of the performance of a system by supervising the remaining capacity of a store data buffer, and performing write to a cache memory when the cache memory is in an unused state. CONSTITUTION:A control circuit 70 supervises a case when a data array 40 is in the idle state, i.e., a case that an access is not requested in a request register 10 and a case whether or not the state that the request necessitating no access to the array 40 is present. Then, when on account of instruction, etc. necessitating no access to the array 40, the cache memory is in the idle state, and there is sufficient storing space of the store data buffer 33, and in addition, when the cache memory is in the unused state the write from a buffer storage device 51 to the cache memory is performed on demand. Thus, a data holding period in the device 51 can be shortened, and the degradation of the performance of the system can be prevented.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a cache memory that stores data read from a main memory in block units, and a cache memory that stores data read from the main memory in blocks at a time. The present invention relates to a cache memory device having a buffer storage device for storing data and a store data buffer for storing store data to a main memory device.

C. Prior Art Conventionally, in this type of cache memory device, writing from the buffer storage device to the cache memory requires reading the next block from the main storage device following the block held in the buffer storage device. [Problem to be Solved by the Invention] The conventional cache memory device described above is limited to the access time until data is transferred from the main memory to the buffer memory. When writing to the cache memory from the device is a newly required block read from the main memory, the cache memory is updated from the time a read request is issued to the main memory until the first data is written to the buffer memory. Since this is performed during idle time, the data may remain in the buffer storage device and not be transferred to the cache memory for a long time, and during this time, the calculation execution unit When there is a store request from , access to the cache memory after that store request is interrupted, and after all writing from the buffer storage device to the cache memory is completed, the store request is executed to the cache memory. Since the cache memory cannot be accessed, the longer data is retained in the buffer storage device, the more chance of encountering a store request, which leads to a decrease in system performance.

[Means for Solving the Problems] A cache memory device of the present invention includes: means for detecting an idle state in which the cache memory is not used; means for monitoring the remaining capacity of the store data buffer; and means for monitoring the remaining capacity of the store data buffer. has a means for activating the transfer of data from the buffer storage device to the cache memory when the amount is greater than or equal to a predetermined amount and an idle state is detected.

[Operation] When the cache memory is in an idle state due to an instruction that does not require access to the cache memory, there is sufficient storage space for the store data buffer, and the cache memory is not in use, data is transferred from the buffer storage device to the cache memory at any time. , the data retention period in the buffer storage device can be shortened and system performance can be prevented from deteriorating.

[Example 1 Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a cache memory device of the present invention.

The request register 10 is a register that holds a request code including the type of access request, instruction content, and validity, and the address of the access request.The request code is sent to the control circuit 70 via a connection 107, and the request code is analyzed and the first Necessary control signals are generated and distributed to each part shown in the figure. On the other hand, request register 1
The address output of 0 is distributed to each section as necessary.

Addresses in the address array 20, which is the address section of the cache memory that stores the correspondence between blocks registered in the cache memory and blocks in the main memory, are read out via the connection 201 by the set address (connection 101), and are sent to the detection circuit. 21, the key address in the request register 10 (connection 102) and the address array 2 are matched.
The V bit (connection 202) indicating the validity of the entry stored in 0 is examined. If the key addresses match and the v bit is on, it is called a found block, and the FDB signal on the connection 211 is turned on, and the control circuit 70
Notify that the target data exists in the cache memory.

The detection circuit 53 detects a block address (connection 106) consisting of a key address and a set address held in the request register 10 and the output of a block address register 52 holding a block address of data registered in the buffer storage device 51. and the entry valid bit (hereinafter referred to as the BEV bit) held in each entry of the buffer storage device 51 in the buffer control buffer 50 is checked, and it is detected that the BEV bit is on and the above block address matches. If so, a buffer storage device match signal (hereinafter referred to as the BBM signal) is notified to the control circuit 70 via the connection 531. Also, the BEV bit is simultaneously output to the control circuit 70 via a connection 501.

When the request register 10 accepts a read request, the control circuit 70 checks the FDB signal and the BBM signal and basically executes the following processing.

(1) When the FDB signal is off. In this case, since the requested data does not exist in the cache memory, the control circuit 70 sends a block read request to the main storage device. Then, until the read data is returned from the main memory, the request register l
0 as is, and register the key address (connection 102) and block address (connection 106) in the request register 10 to the address array 20 and block address register 52, respectively. When the BEV bit according to the previous request is on and valid data exists, the data is transferred via the data fuse 4 line 641 that stores the data in the cache memory and the switching circuit 61. The control circuit 7o also monitors whether the data array 4o is in an idle state, that is, when there is no access request in the request register 10, and whether there is a request that does not require access to the data array 40, , and that there is still room in the buffering state of the store buffer, that is, the buffer storage device 51 to data array 4
When it is detected that the store data buffer does not become full even if priority is given to moving the entry to 0, data is written to the data array 40 from the entry for which the BEV bit in the buffer control buffer 50 is on via the connections 511 and 641, and the write is completed. When finished, the corresponding B in the buffer control buffer 50
Turn off the EV bit.

Further, a block read is a request to transfer one block of the main memory device, and the buffer memory device 51 of this embodiment has a size of 64 bytes, and the data transfer width with the main memory device is g.
Since it is a byte, main memory read data is output eight times. The first main memory read data is registered in the buffer storage device 51 via the switching circuit 63, and at the same time, the data is transferred to the switching circuit 6.
4. The read data is returned to the request source via the switching circuit 62, and the second and subsequent read data are registered in the buffer storage circuit 51.

(2) When the FDB signal is on. In this case, BB
If the M signal is referenced and the BBM signal is off, the switching circuit 6
If the BBM signal is on, the data read from the data array 40 via the data array address (connection 104) via the connection 661 through the block 661 is read from the buffer storage device 51 at the intra-block data array address (connection 105). is switched by the switching circuit 62 and sent back to the request source.

The general read request processing is as described above, but if at the time of the read request, data that is being processed due to a store request remains in the store data buffer 33, and the area of the store is the same area as the read request. , a detection circuit 34 that compares the block address and a detection circuit 35 that compares the intra-block data array address (8-byte address) detect the address data of the store address buffer 31. The block address is determined by connection 311, and the intra-block data array address is determined by connection 312. The block address of the read request (connection 106) and the in-block data array address (connection 105) are compared, and it is detected that there is store data in the same area, and connection 3 is input.
41.

351 to the control circuit 70, the control circuit 70 suspends the processing of the read request until the processing of the store request in progress is completed. When a store request is accepted by the request register, the block address (connection 106) and the intra-block data array address (
The connection 105) is registered in the store address buffer 31, and the store format information that specifies the store format decoded by the control circuit 70 and the V bit (hereinafter referred to as the SAV bit) indicating the validity of the entry in the store data buffer 33 are stored. It is registered in the control buffer 3o. At this time, the SAV bit is registered as on, is transmitted to the detection circuits 34 and 35 and the control circuit 70 via the bus 301, and is turned off when the main store request processing is completed. When the store data (8 bytes) prepared by the arithmetic execution unit (not shown) and the store mask indicating whether or not the store execution is possible in byte units are sent after registering the address of the store request, each store After being registered in the data buffer 33 and store mask buffer 32, the store control buffer 30. store address buffer 31, store mask buffer 32,
The store data buffer 33 is read out at the same time, and the store control buffer 30 is sent to the main memory as a main memory request code.
The information read from the main memory is stored as the main memory request address via the connection 313, the output of the store address buffer 31 is passed through the switching circuit 65, the output of the store mask buffer 32 is stored as the main memory store mask, and the output is stored as the main memory store data. The data buffer 32 is sent, and the processing of the store request ends.

If the FDB signal is on at the time of the store request, writing of the store data to the data array 40 is executed via the connection 331 and the switching circuit 61 prior to sending it to the main memory, or the data is directly switched to the request source. It is sent back via circuit 62. In addition, in the store request processing, it is checked whether the store request address is for a block on the buffer storage device 51, and if the BBM signal is on, the data array is transferred from the buffer storage device 51 prior to the store request processing. 40, entries that have not yet been migrated to the cache memory in the buffer storage device 51 (the BEV bit in the buffer control buffer 50 is on) are migrated, and then the store request is processed and the data array 40 is control is performed to prevent mismatch between the data on the main memory and the data on the main memory.

〔Effect of the invention〕

As explained above, the present invention enables writing from the buffer storage device to the cache memory by writing to the cache memory when there is sufficient storage space in the store buffer and the cache memory is not in use. This has the effect of shortening the period during which the cache memory cannot be accessed due to writing from the device to the cache memory, thereby preventing a decline in system performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a cache memory device of the present invention. DESCRIPTION OF SYMBOLS 10... Request register, 20... Address register, 30... Store control buffer, 31... Store address buffer, 32... Store mask buffer, 33... Store data buffer, 40 ...Data array, 50...Buffer control buffer, 51...Buffer storage device, 52...Block address register, 21.34,3
5.53...Detection circuit, 61.62, 63, 64, 6
5.66...Switching circuit, 70...Control circuit.

Claims (1)

[Claims] 1. A cache memory that stores data read from the main memory in units of blocks, a buffer storage that stores one or more blocks of data read from the main memory at a time, and a main memory. In a cache memory device having a store data buffer for storing store data, the cache memory device includes: means for detecting an idle state in which the cache memory is not used; means for monitoring remaining capacity of the store data buffer; and remaining capacity of the store data buffer. 1. A cache memory device comprising means for activating data transfer from the buffer storage device to the cache memory when the buffer storage device is at least a predetermined amount and an idle state is detected.