JPH01205363A - Direct memory access state decision circuit - Google Patents

Abstract

PURPOSE:To use transfer capacity to the utmost by detecting that plural devices did not transmit a data transfer request to a DMA controller, and shortening the transmission interval of the data transfer request according to a detected result. CONSTITUTION:An inter-memory transfer controller 19 is provided with a state decision circuit 9 and a request generation circuit 10, and supervises a state that disk controllers 5 and 6 perform data transfer with a storage device 2, and controls its own data transfer speed correspondingly to said state. In the circuit 9, when a DMA transfer start signal is inputted, it informs a detecting means 27 that the transfer start signal is inputted. A timing means 26 sends an interval signal to the means 27 at every lapse of definite time, and erases the storage of the input of the transfer start signal. Accordingly, it shortens the transmission interval of the data transfer request which the circuit 10 transmits to the DMA controller 3, and makes the device 19 transfer the data at high speed. Thus, the data transfer capacity of the controller 3 can be used to the utmost.

Description

[Detailed Description of the Invention] [Summary] A direct memory access state determination circuit that controls access requests to its own storage device according to access states to the storage device of a plurality of devices that transfer data in direct memory access mode, The purpose is to make maximum use of the transfer capability of the direct memory access control device.In direct memory access mode, the device is connected to a direct memory access control device that controls multiple devices that transfer data to and from the storage device, and other In a device that switches an interval for sending data transfer requests to a direct memory access control device in response to a direct memory access operation of the device,
timing means for transmitting a signal every time a predetermined period of time elapses; and detection for detecting that the plurality of devices have not sent a data transfer request to the direct memory access control device during the predetermined period of time sent by the timing means. and means for shortening the sending interval of data transfer requests to the direct memory access control device based on the detection result of the detection means.

[Industrial application field]

The present invention relates to a direct memory access state determination circuit that controls access requests to its own storage device according to access states to the storage device of a plurality of devices that transfer data in a direct memory access mode.

For example, a plurality of disk control devices that connect disk devices that perform high-speed data transfer during direct memory access (hereinafter abbreviated as DMA), and an inter-memory transfer control device that transfers data at an arbitrary speed between storage devices. , a DMA control device that operates by connecting these devices, and a processing device that controls all of these devices, in order to make maximum use of the transfer capacity of the DMA control device, it is necessary to The transfer control device is equipped with a status determination circuit to monitor the DMA operation status of the disk control device, and if the disk control device is in operation, increases the sending interval of its own data transfer requests and transfers data at a low speed. If the disk control device is stopped, the data transfer request transmission interval is reduced to perform data transfer at high speed.

In this case, it is necessary to always be able to control the data transfer request sending interval in accordance with the operating state of the disk controller.

[Conventional technology]

FIG. 4 is a block diagram illustrating an example of the system configuration.

Based on instructions from the processing device 1, the DMA control device 3 controls the disk control devices 5 and 6 to transfer data at high speed between the storage device 2 and the disk devices 7 and 8 in direct memory access mode. .

The inter-memory transfer control device 4 reads data from the storage device 2 and performs data transfer with the storage device 2 in order to store the read data in another area of the storage device 2. 10, it monitors the state in which the disk control devices 5 and 6 perform data transfer with the other device 2, and adjusts its own data transfer speed in accordance with the state.

That is, the status determination circuit 9 monitors the status of data transfer between the storage device 2 and the disk controller 5 and/or disk controller 6, and monitors the status of data transfer between the storage device 2 and the disk controller 5 and/or the disk controller 6.
Or, if 6 is in the process of data transfer, the request generation circuit 10 increases the time interval at which it sends a data transfer request to the DMA control device 3, and increases the time during which the DMA control device 3 allocates the bus with the storage device 2. By lengthening the interval, data transfer to and from the storage device 2 is performed at low speed.

Furthermore, when the disk controllers 5 and/or 6 have stopped data transfer, the request generation circuit 10 reduces the request time interval for sending data transfer requests to the DMA controller 3, and connects the storage device 2 at high speed. Transfer data between.

By doing so, it is possible to make maximum use of the data transfer capability of the DMA control device 3.

FIG. 5 is a block diagram explaining the conventional technique, and FIG. 6 is a time chart explaining the operation of FIG.

When the DMA control device 3 receives the DMA request signal DRQ@ from the disk control device 5, it returns a response signal DACK@ as shown in FIG. Also, the DM of the disk control device 6
When the A request signal DRQ■ is received, as shown in FIG.
When the response signal DACK■ to the disk control device 5 reaches its peak, the response signal DACK■ is returned.

When the DMA control device 3 receives the DMA request signal DRQ from the disk control device 5, it turns on the DMA transfer start signal DSTAT and sets it to "1" as shown in FIG. A code that is sent to the AND circuit 13 of and notifies the decoder 11 of the operating device, that is,
It sends out a WCH indicating that it is the disk control device 5.

This code WCH is composed of 2 bits, for example, and is “O”.
0” indicates that it is the disk controller 5, and when the decoder 11 decodes the code WCH, it ORs “1”.
It is sent to the AND circuit 13 via the circuit 12. Therefore, A
The ND circuit 13 sends "1#" to the J terminal of the flip-flop 15, and the flip-flop 15 receives the transfer end notification signal TSTOP from which the DMA control device 3 notifies the end of data transfer.
is sent under the condition that the disk control device is not being sent, and "1" is sent from the Q terminal as a BSY signal indicating that the disk control device is in operation.

Further, when the DMA control device 3 receives the DMA request signal DRQ■ from the disk control device 6, it sends the DMA request signal DRQ as shown in FIG.
A transfer start signal DSTAT is sent to the AND circuit 13 of the state determination circuit 9 of the inter-memory transfer control device 4, and the decoder 1
1, a code notifying the operating device, ie, a WCH indicating that it is the disk control device 6, is sent.

When this code WCH is "0" and "1", the disk controller 6
When the decoder 11 decodes the code WCH, the decoder 11 outputs "1" to the AND circuit 1 via the OR circuit 12.
Send to 3. Therefore, the AND circuit 13 sends "1" to the J terminal of the flip-flop 15, and the flip-flop 15 is set under the condition that the DMA control device 3 has not sent the transfer end notification signal TSTOP to notify the end of data transfer. Then, "1" is sent from the Q terminal as a BSY signal indicating that the disk control device is in operation.

When the flip-flop 15 sends out "l", the multiplexer 16 of the request generation circuit 10 of the inter-memory transfer control device 4 switches the count value set in the counter 17 to a large value. When the counter 17 counts the set count value, it sends out a carry signal TC to the J terminal of the flip-flop 18, thereby causing the flip-flop 18 to enter.

When the flip-flop 18 is set, it sends a DMA request signal DRQ to the DMA control device 3, and when it receives a response signal DACK from the DMA control device 3 at its terminal, it is reset, and the counter 17 sends a carry signal TC to be sent next.
is also set by DM request signal DRQ
It is sent to the A control device 3.

Since the sending interval of this DMA request signal DRQ becomes the sending interval of the carry signal TC of the counter 17 set to a large count value, the storage device 2 of the inter-memory transfer control device 4
The data transfer speed will be low.

Here, for example, when the data transfer of the disk control device 5 is completed, the DMA control device 3 sends the DMA transfer start signal DSTAT and the code WCH notifying the operating device when performing the last data transfer, as shown in FIG. After sending, a transfer end notification signal TSTOP is sent to the AND circuit 14 of the state determination circuit 9 and the disk controllers 5 and 6 at the same time as the response signal DACK■ to notify the end of the transfer.

The AND circuit 14 is connected to the decoder 11 via the OR circuit 12.
Since the flip-flop 15 is also sending out a "1", a '1' is sent to the terminal of the flip-flop 15. Therefore, since both the J terminal and the flip-flop 15 have "1", when a clock is input, "0" is sent out from the Q terminal.

When “O” is input manually, multiplexer 16 outputs counter 1.
Switch the count value set to 7 to a smaller value. Therefore,
As shown in FIG.
Set 8.

When the flip-flop 18 is set, it sends a DMA request signal DRQ to the DMA control device 3 as shown in FIG. is set again by the carry signal TC to be sent next, and sends the DMA request signal DRQ■ to the DMA control device 3.

Since the sending interval of this DMA request signal DRQ becomes the sending interval of the carry signal TC of the counter 17 to which a small count value is sent, the storage device 2 of the inter-memory transfer control device 4
The data transfer speed will be high.

[Problem to be solved by the invention]

In the above method, the completion of data transfer by the disk controller 5 or 6 can only be detected when the transfer end notification signal TSTOP sent by the DMA control device 3 is turned on. The condition for this transfer end notification signal T S T OP to be turned on is that the DMA control device 3 is connected to the processing device 1 shown in FIG.
, the amount of data to be transferred by the disk controller 5 or 6 is specified in advance, and when this amount of data is exceeded,
This occurs only when the processing device 1 issues a stop instruction to the DMA control device 3 during DMA transfer.

In addition to the above conditions, DMA transfer ends when the disk controller 5 or 6 detects that there is no more data to transfer, or when the disk controller 5 or 6 detects an abnormality during data transfer. This is the case. When the disk control devices 5 and 6 detect such a state, they notify the processing device 1 by sending an interrupt signal.

Even if data transfer is interrupted by an interrupt signal from the disk control device 5 or 6 to the processing device 1, the DMA control device 3 detects this state and issues a transfer end notification signal TSTOP.
Therefore, the state determination circuit 9 of the inter-memory transfer control device 4 cannot detect the completion of data transfer of the disk control device 5 or 6 due to an interrupt to the processing device 1, and the state judgment circuit 9 of the inter-memory transfer control device 4 cannot detect the completion of data transfer of the disk control device 5 or 6 due to an interrupt to the processing device 1. There is a problem in that the transfer speed remains low and the transfer capability of the DMA control device 3 cannot be utilized to its fullest extent.

In view of these problems, the present invention provides a means for estimating the completion of data transfer in the disk control device 5 or 6 by interrupting the processing device 1, and turns off the BSY signal sent by the flip-flop 15 to prevent the disk from being transferred. D assumes that the data transfer of the control device 5 or 6 has been completed.
The purpose is to make maximum use of the transfer capability of the MA control device 3.

[Failure to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

The DMA control device 3 controls the disk control devices 5 and 6 to transfer data at high speed between the storage device 2 and the disk devices 7 and 8 shown in FIG. 4 in direct memory access mode.

The inter-memory transfer control device 19 is equipped with the state determination circuit 9 and the request generation circuit 1o as described in FIG. , and adjusts its own data transfer rate accordingly.

The state determination circuit 9 receives the DMA transfer start signal DS shown in FIG.
When the TAT is input, the detection means 27 is made to remember that the transfer start signal has been input.

The timing means 26 sends an interval signal to the detection means 27 every τ after a certain period of time has elapsed, and when the detection means 27 receives this interval signal, it erases the memory in which the transfer start signal was manually input.

When the timing means 26 sends out the next interval signal, the detection means 27 detects the transfer start signal stored in the state judgment circuit 9, if the state judgment circuit 9 has not made it remember that the transfer start signal has been input again. Erase the memory of the signal. That is, the BSY signal shown in FIG. 6 is turned off.

Therefore, the sending interval of data transfer requests sent by the request generation circuit 10 to the DMA control device 3 is reduced, and data transfer is performed at high speed.

[Operation] By configuring as described above, the detection means 27 can detect DMA
The timing means 2 indicates that the transfer start signal DSTAT signal and the code WCH notifying the operating device are not received.
The status determination circuit detects when a certain period of time for data transmission by the disk controller 5 or 6 has elapsed, and recognizes that the disk controller 5 or 6 has run out of data to transfer or has detected an abnormality and has stopped data transfer. It becomes possible to erase the memory of the transfer start signal of No. 9.

Therefore, the request generation circuit 10
The data transfer capability of the DMA control device 3 can be utilized to the maximum by reducing the sending interval of data transfer requests sent to the DMA control device 3 and causing the memory-to-memory transfer control device 19 to transfer data at high speed.

〔Example〕

FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention.
FIG. 3 is a time chart explaining the operation of FIG. 2.

In FIG. 2, the same reference numerals as in FIG. 5 indicate the same functions. When the DMA control device 3 receives the DMA request signal DRQ@ from the disk control device 5, as shown in FIG. A code WCH indicating that the operating device is the disk control device 5 is sent to the decoder 11.

The decoder 11 decodes the code WCH and outputs the OR circuit 1
2, the AND circuit 13 outputs “1”.
m is J of flip-flop 15 and flip-flop 25
As shown in FIG.
5 is set under the condition that the DMA control device 3 does not send out the transfer end notification signal TSTOP, and sends "1" as the BSY signal from the Q terminal. flip flop 2 at the same time
5 is also set, and as shown in FIG. 3, the timer valid signal TDVAL is turned on and 1'' is sent out.

As shown in FIG. 3, the interval timer 21 turns on the interval signal TINT at regular intervals and sends out "1". Therefore, the AND circuit 22 outputs the interval signal T
Since INT and the timer valid signal TDVAL are both turned on, "B" is sent to the terminal of the flip-flop 25, and the flip-flop 25 is reset and turns off the timer valid signal TDVAL as shown in FIG. as “0”
” is sent.

For example, if the disk control device 6 detects an abnormality or the data to be transferred is completed and does not send the DMA request signal DRQ to the DMA control device 3 (as shown in FIG. 3), the DMA control device 3 DMA transfer start signal DSTA
Since T and code WCI-1 are not sent, "1" is not input from the AND circuit 13 to the J terminal of the flip-flop 25, and the timer enable signal TDVAL remains off.

The NOT circuit 23 sends "1" to the AND circuit 24, and the interval timer 21 receives the next interval signal T.
When INT is turned on and "1" is sent out, the AND circuit 24 sends "1" through the OR circuit 20 to the terminal of the flip-flop 15, as shown in FIG. As shown in FIG. 5, the BSY signal is turned off and "0" is sent to the multiplexer 16.As explained in FIG.
When , a large count value is set in the counter 17, and when the BSY signal is "0", a small count value is set in the counter 17.

Therefore, as explained in FIG. 5, while the disk controller 5 is transferring data, the inter-memory transfer control device 19 transfers data at a low speed as shown in FIG. Within the interval, the next D
When no MA request is input to the DMA control device 3, data transfer is performed at high speed.

Here, for example, as shown in FIG. 3, the disk controller 6 sends the DMA request DRQ to the DMA controller 3.
When the data is sent, the memory-to-memory transfer control device 19 lowers the data transfer speed again in the same manner as described above.

Although this embodiment shows one state determination circuit 9 and one direct memory access state determination circuit for two disk control devices 5, 6, it goes without saying that they may be provided for each disk control device.

〔Effect of the invention〕

As described above, the present invention can accurately grasp the data transfer status of the disk control device and always make maximum use of the transfer capability of the DMA control device.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a block diagram of a circuit showing an embodiment of the present invention, Fig. 3 is a time chart explaining the operation of Fig. 2, and Fig. 4 is a block diagram of the principle of the present invention.
5 is a block diagram illustrating an example of a system configuration, FIG. 5 is a block diagram illustrating a conventional technique, and FIG. 6 is a time chart illustrating the operation of FIG. 5. In the figure, 1 is a processing device, 2 is a storage device, 3 is a DMA control device, 4.19 is an inter-memory transfer control device, 5.6 is a disk control device, 7.8 is a disk device, 9
is a state determination circuit, 10 is a request generation circuit, 11 is a decoder, 12.20 is an OR circuit, 13, 14
, 22.24 are AND circuits, 15.18.25 are flip-flops, ]6 is a multiplexer, 17 is a counter, 21 is an interval timer, 23 is a NOT circuit, 2
6 is a timing means. 27 is a detection means.

Claims (1)

[Claims] In direct memory access mode, the device is connected to a direct memory access control device (3) that controls a plurality of devices (5) and (6) that transfer data to and from the storage device (2); In the device (19) for switching the sending interval of data transfer requests to the direct memory access control device (3) in response to the direct memory access operation of the device, the timing means (26) sends a signal every time a certain period of time elapses. ), and detecting that the plurality of devices (5) and (6) have not sent a data transfer request to the direct memory access control device (3) for a certain period of time sent by the timing means (26). a detection means (27), and based on the detection result of the detection means (27), the direct memory access control device (3) shortens the sending interval of data transfer requests to the direct memory access control device (3). circuit.