JPH0120552B2 - - Google Patents

Abstract

PURPOSE:To obtain higher integration density in smaller size memories by making memory status of ''1'' or ''0'' correspond to either existence or absence of depletion layers produced under the channel region with only one impurity diffusion layer provided in each memory cell. CONSTITUTION:A p type silicon substrate 1 is divided by a channel stoppers 1' and field oxide layers 2, and an n<+> layer 3 is formed on the substrate. An insulating layer 5, the floating gate 6, an insulating layer 7 and the control gate 8 are laminated on the channel 4. Under this construction, when electrons exist in the floating gate 6, a small depletion layer 9 exists in the channel 4, but no electrons exist, a larger depletion layer 9' exists in the channel. The depletion layer grows when positive voltage is applied to word terminal W, so that electrons flow from n<+> layer 3 to the depletion layer toward the direction X as indicated by the arrow. Memory status of either ''1'' or ''0'' can be read out by detecting this current. Values of the current is determined by a total of thicknesses of the insulating layers 5, 6 and area of the channel 4.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a nonvolatile semiconductor memory device, and particularly to a floating gate type nonvolatile semiconductor memory device.

Floating type nonvolatile semiconductor memory devices are widely known. In a conventional floating type nonvolatile semiconductor memory device, a source, a drain, and a channel region are formed on a semiconductor substrate, and a floating gate is formed on the channel region with an insulating film interposed therebetween. A control gate is formed thereon with an insulating film interposed therebetween. This device writes:
This is done by injecting a carrier into the floating gate through tunneling or avalanche breakdown. Thus, for example, in an n-channel device, when electrons are injected into the floating gate, the threshold value increases, whereas when electrons are swept out of the floating gate, the threshold value decreases. . These two states correspond to storage states "1" and "0". That is, when a predetermined voltage is applied to the control gate, the on state and off state corresponding to the presence or absence of a channel in the channel region correspond to the memory states "1" and "0".

However, in the conventional type described above, each memory cell requires two impurity diffusion layers, that is, a source region and a drain region, resulting in a large cell area and a problem in that the degree of device integration is low. There is.

There is also a device in which the above-mentioned impurity diffusion layer is made into one, thereby reducing the cell area and thus increasing the degree of integration of the device (see Japanese Patent Laid-Open No. 148341/1983). However, in this case, since the write operation and the erase operation utilize avalanche breakdown, another high-concentration impurity diffusion layer must be provided, resulting in high manufacturing costs. Furthermore, the cell area has not been sufficiently improved, and therefore the degree of integration of the device has not been sufficiently improved.

It is an object of the present invention to provide only one impurity diffusion layer in each memory cell, so that the memory states "1" and "0"
By adjusting the presence or absence of a void layer that occurs under the channel region and performing writing and erasing operations using the tunnel effect, the cell area can be reduced, and the degree of integration can therefore be increased. The aim is to solve problems in form.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a nonvolatile semiconductor memory device as an embodiment of the present invention. In Figure 1,
A relatively thick field insulating film 2 and a channel stop diffusion region 1' are formed on a p-type semiconductor substrate 1. In the active region where field insulating film 1 does not exist, impurity diffusion region 3 and channel region 4 are formed. In this case, the impurity diffusion region 3 is a high concentration n ⁺ diffusion layer obtained by doping with phosphorus (P) or arsenic (As). A first insulating film 5 is formed on the channel region 4, and a floating gate 6 is further formed on the insulating film 5. Further, a second insulating film 7 is formed on the floating gate 6, and a control gate 8 is further formed on the second insulating film 7. In the present invention, in FIG.
A feature is that only one impurity diffusion region 3 is present. In the device shown in FIG. 1, there is also an insulating film, such as a PSG film, covering the entire structure, and wiring connecting each cell, but these are omitted.

Write and erase operations in the device of FIG. 1 are performed using the tunnel effect. When electrons are injected from the semiconductor substrate 1 into the floating gate 6 using the tunnel effect, the potential of the bit line terminal B is set to zero and the potential of the word line terminal W is set to a positive high voltage. Further, when the electrons in the floating gate 6 are swept to the semiconductor substrate 1, the potential of the bit line terminal B is set to a positive voltage, and the potential of the word line terminal W is set to a negative high voltage. Note that such write and erase operations are the same in the case of the conventional type in which two impurity diffusion regions exist.

Next, the reading operation of the apparatus shown in FIG. 1 will be explained. 2A and 2B are schematic cross-sectional views for explaining the read operation of the apparatus of FIG. 1.
Note that the channel stop diffusion layer 1' is omitted. 2A shows a state in which electrons are accumulated in the floating gate 6, and FIG. 2B shows a state in which there are no electrons in the floating gate 6. Note that in FIGS. 2A and 2B, the bit line terminal B is in a floating state, and a predetermined positive voltage (however, relatively low) is applied to the word line terminal W.

As shown in FIG. 2A, a small depletion layer 9 exists in the channel region 4 due to the presence of electrons in the floating gate 6, whereas as shown in FIG. In the absence of electrons, a large depletion layer 9' exists in the channel region 4. Therefore, in FIG. 2B, the moment a positive voltage is applied to the word line terminal W, the depletion layer grows, and electrons flow from the impurity diffusion region 3 toward the depletion layer as shown by the arrow X. Therefore, by detecting the current generated in this manner, the memory state "1" or "0" can be read. In this case, the magnitude of this current is determined by the total thickness of insulating film 5 and insulating film 7 and the area of channel region 4.

FIG. 3 shows a circuit diagram of a sense-up circuit for detecting the current caused by charges flowing into the depletion layer. In Figure 3, Q ₁ , Q ₂ , Q ₃ are gate transistors, Q ₄ , Q ₅ are load transistors, Q ₆ ,
_Q7 is the drive transistor. C schematically shows the depletion layer 9 in FIG. 2A or the depletion layer 9' in FIG. 2B, and DC shows the depletion layer of a dummy cell having the same configuration as in FIG. This is what is shown.

Turn on gate transistors Q ₂ and Q ₃ ,
After setting the voltages of both bit lines connected to the depletion layers C and DC to the same value (VDD-Vth), the gate transistors Q ₂ and Q ₃ are turned off again. After that, when a positive voltage is applied to the gate word line of the dummy cell, for example, in the case of FIG. 2A, the charge injected into the depletion layer DC is larger than the charge injected into the depletion layer C. For,
The bit line connected to depletion layer C is the depletion layer
The voltage will be higher than the bit line connected to DC. Both voltages are immediately transferred to the gates of transistors Q ₄ and Q ₅ , respectively. Here, when V _LE is applied to the gate of transistor Q ₁ , the flip-flop circuit formed by transistors Q ₁ , Q ₄ , Q ₅ , Q ₆ , and Q ₇ is driven, and the potential of output terminal Vo becomes low level. is set and reading is completed.

On the other hand, in the case of Figure 2B, the voltage of the bit line connected to the depletion layer C is lower than that of the bit line connected to the depletion layer DC, and the potential of the output terminal Vo becomes high level. Reading is complete.

As explained above, according to the present invention, since the impurity diffusion region is reduced compared to the conventional type, the degree of integration of the device can be increased, which helps to solve the problems of the conventional type described above. .

[Brief explanation of drawings]

FIG. 1 is a sectional view of a floating type nonvolatile semiconductor memory device as an embodiment of the present invention, and FIG.
2A and 2B are cross-sectional views for explaining the read operation of the device shown in FIG. 1, and FIG. 3 is a circuit diagram of a sense amplifier circuit for sensing the read signal of the device shown in FIG. 1. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 1'... Channel stop diffusion layer, 2... Field insulating film, 3... Impurity diffusion region, 4... Channel region, 5... First insulating film, 6... Floating gate, 7...Second
insulating film, 8... control gate, 9... depletion layer.

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type is provided, a channel region and a unique impurity region of a conductivity type opposite to that of the semiconductor substrate are provided in one element region of the semiconductor substrate, and a flow A floating gate and a control gate are provided on the floating gate through an insulating film, and memory states "1" and "0" are set according to the size of the depletion layer in the channel region, and the control gate is connected to the floating gate. 1. A nonvolatile semiconductor memory device characterized in that a write operation and an erase operation are performed by a tunnel effect.