JPH0120726B2 - - Google Patents
Info
- Publication number
- JPH0120726B2 JPH0120726B2 JP56066312A JP6631281A JPH0120726B2 JP H0120726 B2 JPH0120726 B2 JP H0120726B2 JP 56066312 A JP56066312 A JP 56066312A JP 6631281 A JP6631281 A JP 6631281A JP H0120726 B2 JPH0120726 B2 JP H0120726B2
- Authority
- JP
- Japan
- Prior art keywords
- integrating
- circuit
- resistor
- capacitor
- operational amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03B—APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
- G03B7/00—Control of exposure by setting shutters, diaphragms or filters, separately or conjointly
- G03B7/08—Control effected solely on the basis of the response, to the intensity of the light received by the camera, of a built-in light-sensitive device
- G03B7/081—Analogue circuits
- G03B7/083—Analogue circuits for control of exposure time
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure Control For Cameras (AREA)
Description
【発明の詳細な説明】
本発明はカメラに搭載される電子シヤツター用
積分回路に関するもので、特に受光素子の出力電
流を積分するための積分回路における容量値を電
気回路により等価的に可変させ得る積分回路に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrating circuit for an electronic shutter installed in a camera, and in particular, the capacitance value of the integrating circuit for integrating the output current of a light receiving element can be equivalently varied by an electric circuit. It concerns an integrating circuit.
カメラのシヤツター動作を制御する一つの情報
としてフイルム感度を表わすASA情報がある。
この種の情報を導入する方法としては従来から、
光学的な方法、対数圧縮→加、減算→指数伸
張を行わせるいわゆるアナログ演算方法、及び
積分後の比較器の比較電圧を変える方法等が採用
されている。しかしの方法では機械的であるた
め装置が複雑になり、また調整作業等に高度な技
術が必要になるという欠点があり、の方法は応
答性に問題があつて特に調光ストロボ制御等が困
難であるという問題があり、更にの方法は設定
し得るダイナミツクレンジが狭く、近年要求され
ているような広い範囲に亘つて変化する入力情報
に適合させ得ることは困難であるという欠点があ
つた。 One type of information that controls the shutter operation of a camera is ASA information that indicates film sensitivity.
Traditional methods for introducing this type of information include:
Optical methods, so-called analog calculation methods in which logarithmic compression→addition, subtraction→exponential expansion, and methods of changing the comparison voltage of a comparator after integration have been adopted. However, method (2) has the disadvantage that the device is complicated because it is mechanical, and advanced technology is required for adjustment work, etc., and method (2) has problems with responsiveness, making it particularly difficult to control dimming strobes, etc. In addition, other methods have the disadvantage that the dynamic range that can be set is narrow, making it difficult to adapt to input information that changes over a wide range as has been required in recent years. .
本発明は上記従来回路の欠点を除去し、極めて
簡単な回路で積分回路の積分時定数を決定してい
るコンデンサの容量値を可変させ得るシヤツター
用積分回路を提供するものである。 The present invention eliminates the drawbacks of the conventional circuit described above and provides an integrating circuit for a shutter that can vary the capacitance value of the capacitor that determines the integration time constant of the integrating circuit with an extremely simple circuit.
本発明の電子シヤツター用積分回路は、受光素
子の出力電流を積分してシヤツター制御のための
信号を形成する積分回路において、その出力が上
記シヤツター制御のための信号となる、フオロワ
接続された演算増幅器と、該演算増幅器の出力端
と基準電位間に直列接続された第１の抵抗及び第
２の抵抗と、受光素子の出力電流を積分するため
の積分用コンデンサであつて、上記演算増幅器の
他方の入力端と、上記第１の抵抗と第２の抵抗の
結合点との間に接続された積分用コンデンサとを
設けて成ることを特徴とするものである。 The integrator circuit for electronic shutter of the present invention is an integrator circuit that integrates the output current of a light-receiving element to form a signal for shutter control, and has a follower-connected calculation whose output becomes the signal for shutter control. an amplifier, a first resistor and a second resistor connected in series between the output terminal of the operational amplifier and a reference potential, and an integrating capacitor for integrating the output current of the light-receiving element; The present invention is characterized in that it includes an integrating capacitor connected between the other input terminal and the connection point of the first resistor and the second resistor.
次に実施例を挙げて本発明を詳細に説明する。 Next, the present invention will be explained in detail with reference to Examples.
まず第１図は従来から用いられているこの種の
積分回路で、入射光を検出して光量に対応した光
電流を出力する受光素子PDが設けられている。
受光素子PDの両端には極めて高い入力インピー
ダンス特性をもつ演算増幅器OPが接続され、該
演算増幅器OPの出力Voutが積分出力と導出さ
れ、フイルム感度情報等のシヤツター制御のため
の比較電圧が予め与えられた比較回路（図示せ
ず）に与えられてシヤツターを作動させるための
マグネツトに動作電流を供給する。受光素子PD
に接続されたコンデンサＣは積分用コンデンサ
で、コンデンサＣの他端は接地レベルに接続され
ている。トリガスイツチSWが閉じた状態では受
光素子PDの光電流はスイツチSWを介して基準
電位Vref（例えば接地レベル）に流れ、コンデン
サＣ側には流れないため積分されることはない。
しかし露光制御のためにトリガスイツチSWが開
かれると、光電流ｉはコンデンサＣに流れて積分
され、対応する積分出力が演算増幅器OPの出力
端から導出される。閉じた状態のトリガスイツチ
SWを開に変化させてからｔ時間後における出力
電圧Voutは、受光素子PDの出力電流を−ｉとす
ると次式で表わすことができる。 First, FIG. 1 shows this type of integrating circuit that has been used in the past, and is provided with a light receiving element PD that detects incident light and outputs a photocurrent corresponding to the amount of light.
An operational amplifier OP with extremely high input impedance characteristics is connected to both ends of the photodetector PD, and the output Vout of the operational amplifier OP is derived as an integral output, and a comparison voltage for shutter control such as film sensitivity information is provided in advance. A comparator circuit (not shown) supplied with an operating current is supplied to a magnet for operating the shutter. Photodetector PD
A capacitor C connected to is an integrating capacitor, and the other end of the capacitor C is connected to ground level. When the trigger switch SW is closed, the photocurrent of the photodetector PD flows to the reference potential Vref (eg, ground level) via the switch SW, and does not flow to the capacitor C side, so it is not integrated.
However, when the trigger switch SW is opened for exposure control, the photocurrent i flows into the capacitor C and is integrated, and a corresponding integrated output is derived from the output of the operational amplifier OP. Trigger switch in closed position
The output voltage Vout at time t after the SW is changed to open can be expressed by the following equation, assuming that the output current of the light receiving element PD is -i.
Vo＝Vref−１／Ｃ∫t pidt (1)
Vrefは最初にコンデンサＣに充電されていた
電圧を意味する。 Vo=Vref-1/ C∫t p idt (1) Vref means the voltage initially charged in the capacitor C.
第２図は本発明による一実施例を示す電気回路
図で、本発明においては演算増幅器OPの出力端
と接地レベル間に、直列に接続された抵抗R1及
び抵抗R2が設けられ、抵抗R1と抵抗R2の結合点
Ｑに積分用コンデンサＣの他端が接続されて構成
されている。即ち抵抗R1及びR2を設けて、両抵
抗の結合点ＱにコンデンサＣの他端を接続するこ
とによつて積分回路における積分時定数を決定す
る容量値を等価的に可変させる。次に積分容量が
変わることを第２図の実施例回路に基いて説明す
る。 FIG. 2 is an electric circuit diagram showing an embodiment of the present invention. In the present invention, a resistor R 1 and a resistor R 2 are connected in series between the output terminal of the operational amplifier OP and the ground level. The other end of the integrating capacitor C is connected to the connection point Q between R 1 and the resistor R 2 . That is, by providing resistors R 1 and R 2 and connecting the other end of a capacitor C to the connection point Q of both resistors, the capacitance value that determines the integration time constant in the integrating circuit is equivalently varied. Next, the change in integral capacitance will be explained based on the embodiment circuit shown in FIG.
出力電圧Voutは、コンデンサＣに充電された
電圧と結合点Ｑの電位との和によつて得られるた
め、
Vo＝R2／R2＋R1Vref−１／Ｃ∫t pidt＋R1／R2＋R1Vo
従つてVo＝Vref−１／R2／R2＋R1Ｃ∫t pidt (2)
となる。R2／R2＋R1Vrefは最初にコンデンサＣに充
電されていた電圧を意味する。 Since the output voltage Vout is obtained by the sum of the voltage charged in the capacitor C and the potential at the node Q, Vo=R 2 /R 2 +R 1 Vref-1/C∫ t p idt + R 1 /R 2 +R 1 Vo Therefore, Vo=Vref-1/R 2 /R 2 +R 1 C∫ t p idt (2). R 2 /R 2 +R 1 Vref means the voltage initially charged in capacitor C.
上記(1)式及び(2)式から明らかなように、第２図
の回路においては、積分用コンデンサＣの他端を
直ちに接地した積分回路に比べて、積分容量は等
価的にR2／R2＋R1Ｃに減少したことが判る。抵抗R1
とR2の比を変えることによつて容量値の変化さ
せ得る割合は変えることができ、上記積分出力が
一方の入力信号として与えられる比較回路におい
て、比較のための他方の入力情報の種類又は入力
情報の信号レベル等に応じて、抵抗の比率を適宜
設定することにより、積分回路の機能を一層高め
て入力信号の処理範囲を拡げることができる。抵
抗R1，R2の一方を可変抵抗器で構成し、入力情
報に対応させて抵抗値を変化させることもでき
る。 As is clear from equations (1) and (2) above, in the circuit shown in Figure 2, compared to the integrating circuit in which the other end of the integrating capacitor C is immediately grounded, the integrating capacitance is equivalently R 2 / It can be seen that the value has decreased to R 2 +R 1 C. By changing the ratio of resistors R 1 and R 2 , the rate at which the capacitance value can be changed can be changed. By appropriately setting the ratio of the resistors depending on the type of the input signal or the signal level of the input information, it is possible to further enhance the function of the integrating circuit and expand the processing range of the input signal. It is also possible to configure one of the resistors R 1 and R 2 with a variable resistor, and change the resistance value in response to input information.
前記実施例は受光素子と別途に積分用コンデン
サを設けた回路を挙げて説明したが、第３図に示
すように特別にコンデンサを接続することなく受
光素子PD自身がもつ容量特性を利用して回路を
構成することもできる。 The above embodiment has been explained using a circuit in which a light receiving element and a separate integrating capacitor are provided, but as shown in Fig. 3, it is possible to utilize the capacitance characteristics of the light receiving element PD itself without connecting a special capacitor. It is also possible to configure a circuit.
以上のように本発明によれば、極めて簡単な回
路を付加するのみで積分回路の容量値を等価的に
可変させることができ、積分回路の融通性を高め
て広い範囲の入力情報を処理し得る回路を得るこ
とができ、特に限られたスペース内に納められ且
つ高い精度が要求されるカメラのシヤツター制御
のための積分回路に有用なものとなる。 As described above, according to the present invention, it is possible to equivalently vary the capacitance value of the integrating circuit by simply adding an extremely simple circuit, increasing the flexibility of the integrating circuit and processing a wide range of input information. This circuit is particularly useful for integrating circuits for shutter control of cameras that are housed in a limited space and require high precision.
第１図は従来の積分回路を示す図、第２図は本
発明による一実施例を示す電気回路図、第３図は
本発明による他の実施例を示す電気回路図であ
る。
PD：受光素子、OP：演算増幅器、Ｃ：積分用
コンデンサ、R1，R2：抵抗。
FIG. 1 is a diagram showing a conventional integrating circuit, FIG. 2 is an electric circuit diagram showing one embodiment according to the present invention, and FIG. 3 is an electric circuit diagram showing another embodiment according to the present invention. PD: Photodetector, OP: Operational amplifier, C: Integrating capacitor, R 1 , R 2 : Resistor.
Claims (1)
御のための信号を形成する積分回路において、 その出力が上記シヤツター制御のための信号と
なる、フオロワ接続された演算増幅器と、 該演算増幅器の出力端と基準電位間に直列接続
された第１の抵抗及び第２の抵抗と、 受光素子の出力電流を積分するための積分用コ
ンデンサであつて、上記演算増幅器の他方の入力
端と、上記第１の抵抗と第２の抵抗の結合点との
間に接続された積分用コンデンサとを設けて成る
ことを特徴とする電子シヤツター用積分回路。[Scope of Claims] 1. In an integrating circuit that integrates the output current of a light-receiving element to form a signal for shutter control, an operational amplifier connected as a follower whose output becomes a signal for shutter control; A first resistor and a second resistor connected in series between the output terminal of the operational amplifier and a reference potential, and an integrating capacitor for integrating the output current of the light receiving element, the other input of the operational amplifier. 1. An integrating circuit for an electronic shutter, comprising: an integrating capacitor connected between the first resistor and the second resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6631281A JPS57179823A (en) | 1981-04-28 | 1981-04-28 | Integrating circuit for electronic shutter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6631281A JPS57179823A (en) | 1981-04-28 | 1981-04-28 | Integrating circuit for electronic shutter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57179823A JPS57179823A (en) | 1982-11-05 |
| JPH0120726B2 true JPH0120726B2 (en) | 1989-04-18 |
Family
ID=13312175
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6631281A Granted JPS57179823A (en) | 1981-04-28 | 1981-04-28 | Integrating circuit for electronic shutter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57179823A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS634225A (en) * | 1986-06-24 | 1988-01-09 | Asahi Optical Co Ltd | Gain switching device for photometric amplifier |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6230013Y2 (en) * | 1976-07-30 | 1987-08-01 | ||
| JPS5333442U (en) * | 1976-08-30 | 1978-03-23 |
-
1981
- 1981-04-28 JP JP6631281A patent/JPS57179823A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57179823A (en) | 1982-11-05 |
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