JPH0120727B2 - - Google Patents
Info
- Publication number
- JPH0120727B2 JPH0120727B2 JP56066313A JP6631381A JPH0120727B2 JP H0120727 B2 JPH0120727 B2 JP H0120727B2 JP 56066313 A JP56066313 A JP 56066313A JP 6631381 A JP6631381 A JP 6631381A JP H0120727 B2 JPH0120727 B2 JP H0120727B2
- Authority
- JP
- Japan
- Prior art keywords
- operational amplifier
- resistor
- transistor
- output
- integrating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03B—APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
- G03B7/00—Control of exposure by setting shutters, diaphragms or filters, separately or conjointly
- G03B7/08—Control effected solely on the basis of the response, to the intensity of the light received by the camera, of a built-in light-sensitive device
- G03B7/081—Analogue circuits
- G03B7/083—Analogue circuits for control of exposure time
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure Control For Cameras (AREA)
Description
【発明の詳細な説明】
本発明はカメラ用電子シヤツター積分回路に関
するもので、特に積分出力電圧値が予め設定され
たレベルに達した状態で積分時定数を等価的に変
えて、シヤツター動作制御時におけるフイルム感
度情報等の入力情報に対して広い範囲の情報を処
理し得る積分回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic shutter integrator circuit for cameras, and in particular to an electronic shutter integrator circuit for controlling shutter operation by equivalently changing an integral time constant when an integral output voltage value reaches a preset level. The present invention relates to an integrating circuit that can process a wide range of input information such as film sensitivity information.
近年開発されている一眼レフカメラでは
ASA3200というような大きなASAをもつものに
も対応できるようにシヤツター制御機構が工夫さ
れている。しかし実用されているカメラにおい
て、設定し得る電圧のダイナミツクレンジには限
度があり、上記のような広い範囲をもつASAの
全範囲に亘つて同じ時定数で積分回路を構成した
場合には、ASAの大きいところでは電圧の範囲
が非常に狭く、また小さいレベルの電圧値として
しか得られず、適正なフイルム感度情報とはなら
ず誤動作を起こす惧れがあつた。そのため従来か
ら採られている方式は光電流の積分回路に予め容
量値の異なるコンデンサを用意し、フイルム感度
情報に応じてこれ等を切り換えて時定数の異なる
状態を作り出し、光電流による積分回路の積分時
定数を切り換えて対応していた。しかし上記コン
デンサの切換えによる方式は回路が複雑で、電子
回路で構成されたシヤツター制御回路として好ま
しいものとはいえなかつた。 Single-lens reflex cameras that have been developed in recent years
The shutter control mechanism has been devised to be compatible with large ASA models such as the ASA3200. However, in cameras that are in practical use, there is a limit to the dynamic range of voltage that can be set, and if an integrating circuit is configured with the same time constant over the entire ASA range as described above, Where the ASA is large, the voltage range is very narrow, and only small voltage values can be obtained, which may not provide proper film sensitivity information and may cause malfunctions. Therefore, the conventional method used is to prepare capacitors with different capacitance values in advance for the photocurrent integration circuit, and to switch these capacitors according to the film sensitivity information to create states with different time constants. This was handled by switching the integration time constant. However, the above-mentioned method using capacitor switching has a complicated circuit and is not suitable for a shutter control circuit composed of electronic circuits.
本発明は上記従来のシヤツター用積分回路の問
題点に鑑みてなされたもので、受光素子からの光
電流による積分回路の時定数を、積分出力電圧が
予め設定されたレベルに達した状態で自動的に等
価的に切り換えて大きいASA情報等についても
導入を容易にした積分回路を提供するものであ
る。本発明の電子シヤツター用積分回路は、受光
素子の出力電流を積分してシヤツター制御のため
の信号を形成する積分回路において、その出力が
上記シヤツター制御のための信号となる、フオロ
ワ接続された第１の演算増幅器と、該第１の演算
増幅器の出力端と基準電位間に直列接続された第
１の抵抗及び第２の抵抗と、受光素子の出力電流
を積分するための積分用コンデンサであつて、上
記第１の演算増幅器の他方の入力端と、上記第１
の抵抗と第２の抵抗の結合点との間に接続された
積分用コンデンサと、エミツタが上記結合点に接
続され、コレクタが上記基準電位に接続されたト
ランジスタ、非反転端子に所定の電位が与えら
れ、反転端子が上記トランジスタのエミツタに接
続されると共に、出力端が上記トランジスタのベ
ースに接続された第２の演算増幅器とを設けて成
ることを特徴するものである。次に実施例を挙げ
て本発明を詳細に説明する。 The present invention has been made in view of the above-mentioned problems of the conventional integrating circuit for shutters. The present invention provides an integration circuit that can be easily introduced even for large ASA information etc. by switching in an equivalent manner. The integrator circuit for an electronic shutter of the present invention is an integrator circuit that integrates the output current of a light receiving element to form a signal for shutter control, and a follower-connected integrator circuit whose output becomes the signal for shutter control. a first operational amplifier, a first resistor and a second resistor connected in series between the output terminal of the first operational amplifier and a reference potential, and an integrating capacitor for integrating the output current of the light receiving element; and the other input terminal of the first operational amplifier and the first operational amplifier.
an integrating capacitor connected between the connecting point of the resistor and the second resistor, a transistor whose emitter is connected to the connecting point and whose collector is connected to the reference potential, and a predetermined potential is applied to the non-inverting terminal. and a second operational amplifier whose inverting terminal is connected to the emitter of the transistor and whose output terminal is connected to the base of the transistor. Next, the present invention will be explained in detail with reference to Examples.
第１図においてPDは受光素子で、外部光が直
接或いはシヤツター面、フイルム面からの反射し
た光として与えられ、入射光量に基いた光電流ｉ
を出力する。上記受光素子PDの両端は第１演算
増幅器OP1の入力端に接続され、第１演算増幅器
OP1の出力端は積分出力電圧Vo1として比較器
Comに与えられている。該比較器Comはシヤツ
ター駆動のためのマグネツトを制御するための信
号を発生する役目を果し、他方の入力端には比較
の基準となる所望のフイルム感度情報を与える電
圧VASAが入力されている。上記受光素子PDのア
ノード側が接続された第１演算増幅器OP1の非反
転端子（＋）はトリガスイツチSW及び積分用コ
ンデンサＣに接続されている。尚積分用コンデン
サＣは受光素子自身の接合容量を利用することも
できる。積分用コンデンサＣの他端は、第１演算
増幅器OP1の出力端と接地レベル間に接続された
抵抗R1と抵抗R2の結合点Ｙに接続されている。
結合点Ｙは第２演算増幅器OP2の反転端子（−）
に接続されると共にPNPトランジスタTrのエミ
ツタ側に接続されている。該トランジスタTrの
ベースは第２演算増幅器OP2の出力が与えられ、
コレクタは接地レベルに接続されている。上記第
２演算増幅器OP2の非反転端子（＋）側には、積
分時定数を変えるための電圧レベルVaが与えら
れる。ここで電圧Vaは後述するように上記抵抗
R1及びR2の値によつて結合点Ｙの電位を
R1＋R2／R2Vaに固定させる。 In Figure 1, PD is a photodetector that receives external light either directly or as reflected light from the shutter surface or film surface, and generates a photocurrent i based on the amount of incident light.
Output. Both ends of the photodetector PD are connected to the input terminals of the first operational amplifier OP1 , and the first operational amplifier OP1
The output end of OP 1 is used as an integrated output voltage Vo 1 as a comparator
Com is given. The comparator Com serves to generate a signal for controlling the magnet for driving the shutter, and the other input terminal receives a voltage VASA that provides desired film sensitivity information as a reference for comparison. There is. The non-inverting terminal (+) of the first operational amplifier OP1 to which the anode side of the photodetector PD is connected is connected to the trigger switch SW and the integrating capacitor C. Incidentally, the junction capacitance of the light receiving element itself can also be used as the integrating capacitor C. The other end of the integrating capacitor C is connected to a node Y between a resistor R1 and a resistor R2 connected between the output end of the first operational amplifier OP1 and the ground level.
Connection point Y is the inverting terminal (-) of the second operational amplifier OP 2
It is connected to the emitter side of the PNP transistor Tr. The base of the transistor Tr is given the output of the second operational amplifier OP2 ,
The collector is connected to ground level. A voltage level Va for changing the integration time constant is applied to the non-inverting terminal (+) side of the second operational amplifier OP2 . Here, the voltage Va is the resistance above as described later.
The potential of the connection point Y is determined by the values of R 1 and R 2 .
Fix it to R 1 + R 2 /R 2 Va.
次に上記積分回路の動作を説明する。一端が接
地レベルに接続されているトリガスイツチSWが
閉じられた露光開始前の状態では、第１演算増幅
器の出力Vo1は接地電位となつており、受光素子
PDの出力電流ｉはトリガスイツチSW側に流れ
て積分動作は行われない。次にトリガスイツチ
SWを開にすると、受光素子の出力電流ｉは積分
用コンデンサＣ側に流れて積分が開始される。積
分時間の経過に伴つて第１演算増幅器OP1の出力
端の電位Vo1が次第に変化し、抵抗R1，R2間の
結合点Ｙの電位もまた変化する。結合点Ｙの電位
VYが、第２演算増幅器OP2の非反転端子（＋）
に与えられた電位Vaに達するまでは、第２演算
増幅器OP2及びトランジスタTr共にカツトオフ
状態にあり、積分特性に影響はない。上記積分動
作において、トリガスイツチSWが開かれてから
ｔ時間経過後の積分用コンデンサＣの両端電位は
次式で与えられる。 Next, the operation of the above integration circuit will be explained. When the trigger switch SW, one end of which is connected to the ground level, is closed and before exposure starts, the output Vo 1 of the first operational amplifier is at the ground potential, and the light receiving element
The output current i of the PD flows to the trigger switch SW side and no integral operation is performed. Next, trigger switch
When SW is opened, the output current i of the light receiving element flows to the integrating capacitor C side and integration is started. As the integration time passes, the potential Vo 1 at the output terminal of the first operational amplifier OP 1 gradually changes, and the potential at the node Y between the resistors R 1 and R 2 also changes. Potential of connection point Y
V Y is the non-inverting terminal (+) of the second operational amplifier OP 2
The second operational amplifier OP2 and the transistor Tr are both in a cut-off state until the potential Va applied to the second operational amplifier OP2 is reached, and the integral characteristics are not affected. In the above integration operation, the potential across the integration capacitor C after time t has elapsed since the trigger switch SW was opened is given by the following equation.
１／Ｃ∫t pidt＝ｉ・ｔ／Ｃ (1)
一方第１演算増幅器OP1の出力の電位をVo1と
すると、
Vo1＝Vo1×R2／R1＋R2＋ｉ・ｔ／Ｃ
となるので、結局
Vo1＝R1＋R2／R1・ｉ・ｔ／Ｃ (2)
となり、積分用コンデンサＣの他端を直ちに接地
した場合に比べて容量の値が等価的にR1／R1＋R2倍
になつたことに相当する。第１演算増幅器OP1の
出力電圧がR1＋R2／R2Vaの値に達すると結合点Ｙ
の電位はVaとなり、第２演算増幅器OP2及びト
ランジスタTrはカツトオフ状態から能動状態に
遷移し、出力電圧が更に上昇した場合にもトラン
ジスタTrのエミツタ電位、即ち結合点Ｙの電位
を第２演算増幅器OP2に与えられているVaに固
定する。上記(1)式から出力電圧Vo1が上記
R1＋R2／R2Vaに達する時間taはR1＋R2／R1 ｉ・ta／Ｃ
＝R1＋R2／R2Vaより
ta＝Ｃ・１／ｉ・R1／R2Va
となるので、出力電圧Vo1がR1＋R2／R2Vaを越えた
場合の時間ｔと出力電圧Vo1の関係は次式で与え
られる
Vo1＝R1＋R2／R2Va＋１／Ｃ∫t C/i 1/C∫ t p idt=i・t/C (1) On the other hand, if the potential of the output of the first operational amplifier OP 1 is Vo 1 , then Vo 1 =Vo 1 ×R 2 /R 1 +R 2 +i・t/ Therefore, in the end, Vo 1 = R 1 + R 2 /R 1・i・t/C (2) Compared to the case where the other end of the integrating capacitor C is immediately grounded, the capacitance value is equivalently R This corresponds to 1 /R 1 + R doubling . When the output voltage of the first operational amplifier OP 1 reaches the value R 1 + R 2 /R 2 Va, the potential at the node Y becomes Va, and the second operational amplifier OP 2 and the transistor Tr transition from the cut-off state to the active state. Even if the output voltage further increases, the emitter potential of the transistor Tr, that is, the potential at the node Y, is fixed at Va applied to the second operational amplifier OP2 . From equation (1) above, the output voltage Vo 1 is
The time ta to reach R 1 +R 2 /R 2 Va is R 1 +R 2 /R 1 i・ta/C = R 1 +R 2 /R 2 Va, so ta=C・1/i・R 1 /R 2 Va Therefore, when the output voltage Vo 1 exceeds R 1 + R 2 /R 2 Va, the relationship between the time t and the output voltage Vo 1 is given by the following formula: Vo 1 = R 1 + R 2 / R 2 Va + 1/C∫ tC /i
Claims (1)
御のための信号を形成する積分回路において、 その出力が上記シヤツター制御のための信号と
なる、フオロワ接続された第１の演算増幅器と、 該第１の演算増幅器の出力端と基準電位間に直
列接続された第１の抵抗及び第２の抵抗と、 受光素子の出力電流を積分するための積分用コ
ンデンサであつて、上記第１の演算増幅器の他方
の入力端と、上記第１の抵抗と第２の抵抗の結合
点との間に接続された積分用コンデンサと、 エミツタが上記結合点に接続され、コレクタが
上記基準電位に接続されたトランジスタと、 非反転端子に所定の電位が与えられ、反転端子
が上記トランジスタのエミツタに接続されると共
に、出力端が上記トランジスタのベースに接続さ
れた第２の演算増幅器とを設けて成ることを特徴
とする電子シヤツター用積分回路。[Scope of Claims] 1. In an integrating circuit that integrates the output current of a light receiving element to form a signal for shutter control, a first calculation unit connected as a follower whose output becomes a signal for shutter control; an amplifier; a first resistor and a second resistor connected in series between the output terminal of the first operational amplifier and a reference potential; and an integrating capacitor for integrating the output current of the light-receiving element; an integrating capacitor connected between the other input terminal of the first operational amplifier and a connecting point between the first resistor and the second resistor, an emitter connected to the connecting point, and a collector connected to the reference point; a transistor connected to an electric potential, and a second operational amplifier whose non-inverting terminal is applied with a predetermined electric potential, whose inverting terminal is connected to the emitter of the transistor, and whose output terminal is connected to the base of the transistor. An integral circuit for an electronic shutter, characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6631381A JPS57179824A (en) | 1981-04-28 | 1981-04-28 | Integration circuit for electronic shutter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6631381A JPS57179824A (en) | 1981-04-28 | 1981-04-28 | Integration circuit for electronic shutter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57179824A JPS57179824A (en) | 1982-11-05 |
| JPH0120727B2 true JPH0120727B2 (en) | 1989-04-18 |
Family
ID=13312205
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6631381A Granted JPS57179824A (en) | 1981-04-28 | 1981-04-28 | Integration circuit for electronic shutter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57179824A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2858232B2 (en) * | 1995-10-12 | 1999-02-17 | 株式会社スワニー | Suitcase on casters |
| JP2938818B2 (en) * | 1996-10-21 | 1999-08-25 | 株式会社スワニー | bag |
| JP2802914B2 (en) * | 1996-11-08 | 1998-09-24 | 株式会社スワニー | Luggage on casters |
| FR2755590B1 (en) | 1996-11-08 | 2000-04-07 | Swany Corp | BAG EQUIPPED WITH WHEELS |
| JP2901932B2 (en) | 1997-01-07 | 1999-06-07 | 株式会社スワニー | bag |
| WO2003099056A1 (en) | 2002-05-24 | 2003-12-04 | Yoshiaki Tamura | Suitcase with foldable chair |
| JP3793174B2 (en) | 2003-05-21 | 2006-07-05 | 株式会社スワニー | Castor with casters |
| JP4276594B2 (en) | 2004-08-04 | 2009-06-10 | 株式会社スワニー | Caster with casters |
| EP2082664A2 (en) | 2008-01-28 | 2009-07-29 | Swany Corporation | Wheeled luggage and base-and-frame assembly therefor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6230013Y2 (en) * | 1976-07-30 | 1987-08-01 | ||
| JPS5333442U (en) * | 1976-08-30 | 1978-03-23 |
-
1981
- 1981-04-28 JP JP6631381A patent/JPS57179824A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57179824A (en) | 1982-11-05 |
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