JPH01207965A - Manufacture of solid-state image sensor - Google Patents

Abstract

PURPOSE:To cause the manufacturing process of a sensor to be performed at a low temperature and shorten its manufacturing time, by forming two kinds of P-type well layers consisting of a P-type impurity layer which is formed on an N-type semiconductor substrate as well as a P-type epitaxial layer which performs an epitaxial growth on the foregoing impurity layer. CONSTITUTION:As a P<+> type buried diffusion layer 10 on an N-type semiconductor substrate 1 repeats often thermal treatment processes, an auto-doping phenomenon takes place at a P-type epitaxial layer 9 and each impurity having a size of the order of several micron meters comes up to the surface. The P-type well layers having two kinds of junction depths are formed by making the P-type epitaxial layer 9 grow on the P-type impurity layer 10 which is provided on the N-type semiconductor substrate. As the P-type well layers, in this way, are formed without performing an ion implantation process as well as a heat treatment at a high temperature for a long time, the manufacturing process is shortened exceedingly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a solid-state imaging device used as a light receiving portion of a solid-state imaging device, such as an IC sensor of a video camera.

[Prior Art] Conventionally, this type of solid-state image sensor device is disclosed in the following document entitled ``rCCD Image Sensor Process''.

■Published by Press Journal “Sem1conduc”
torWorld 1987.4 pl, 06-11
0 That is, this solid-state image sensing device photoelectrically converts an optical signal into a P/N type light-receiving diode, and sequentially converts it into CC.
A D (Charge Coupled Device) element transfers a signal to an output section.

FIG. 3 shows a cross-sectional explanatory diagram of an imaging section (light-receiving cell) in a conventional solid-state imaging device.

A normal method for manufacturing a solid-state imaging probe is to form P-well layers 2 and 3 on an N-type semiconductor substrate 1 by ion implantation and heat treatment.

In a solid-state image sensor, two types of P-well layers are generally provided for "sucking out" excess light called oats 1-flow drain, and P-well layers (2) and 3 in the figure are ) The junction depth is formed to be shallower than in 2.

After forming the P-well layer, the oxide film 4 is formed using the LOCAL Oxidati method (LOCAL Oxidati) for isolation between solid-state image sensors.
The gate oxide film 5 of the MOS capacitor is then formed by a thermal oxidation method.

Furthermore, in the charge transfer section, N is used to form a buried channel type CCD.
A type impurity layer 6 is formed in a predetermined region by ion implantation, a polysilicon film 7 which will later become a gate electrode of the MOS is formed, and an N type impurity layer 8 forming a P/N junction of the light receiving part is formed by ion implantation. It will be established at

[Problems to be Solved by the Invention] However, the conventional solid-state image sensor device having the above configuration has the following problems.

(a) Since two types of P-well layers with different depths are required on the N-type semiconductor substrate, providing them requires two steps: an ion implantation step and a heat treatment step, which increases manufacturing costs and increases the number of steps. This causes a decrease in yield.

(b) In the conventional light receiving area, for intense incident light,
In order to prevent the blooming phenomenon, it is essential to form the P-well layer shallowly.

(c) Also, as the degree of integration of the cell region of a solid-state imaging device increases, impurities in the deep P-well region invade the shallow P-well region, increasing the impurity concentration and deepening the P-well region. It becomes difficult to form a P-well region.

(d) In order to obtain two types of P-well layers at predetermined depths from an N-type semiconductor substrate, they must be formed by heat treatment at high temperatures and for a long time, making it difficult to integrate devices. In addition, crystal strain generated during high-temperature heat treatment deteriorates the characteristics of the device and tends to cause local defects such as white noise.

(e) Electrons generated in the depletion layer in the P-well layer (2) due to long wavelength light easily leak into the charge transfer section of the CCD, and smear (scattering of incident light and lateral diffusion of carriers causes charges to directly transfer to the CCD). This tends to lead to characteristic deterioration, which is a phenomenon called "white vertical stripes" that appear on the top and bottom of bright objects, significantly degrading image quality.

This invention was made in order to solve the above-mentioned problems in the manufacturing process and the characteristics of the device.
Another object of the present invention is to provide a method for manufacturing a solid-state image sensor with excellent device characteristics.

[Means for Solving the Problems] A solid-state imaging device according to the present invention includes a method for forming a P-well layer of a solid-state imaging device, including the step of forming a P-type impurity layer on a portion of an N-type semiconductor substrate; A step of forming a P-type epitaxial layer or an N-type epitaxial layer on the P-type impurity layer on the semiconductor substrate and the N-type semiconductor substrate, a step of providing a light receiving section and a charge transfer section on the P-type epitaxial layer, or a step of forming an N-type impurity layer on the P-type epitaxial layer. A method for manufacturing a solid-state imaging device, comprising the steps of forming a P-well layer in an epitaxial layer, and providing a light-receiving section and a charge transfer section on the P-well layer.

[Function] The method for manufacturing a solid-state image sensor according to the present invention uses two conventional P
The well layer is formed of a P-type impurity layer provided on an N-type semiconductor substrate and a P-type epitaxial layer epitaxially grown above the P-type impurity layer.

With this configuration, it is possible not only to lower the manufacturing process temperature and shorten the manufacturing time, but also to reduce thermal distortion to the crystal caused by high-temperature, long-term heat treatment, improving device characteristics and improving device characteristics compared to conventional P-type There is no lateral diffusion due to impurities, and device miniaturization can be achieved.

Next, embodiments of the Nikono invention will be described.

[Example] FIG. 1 is an explanatory cross-sectional view of a cell of a solid-state image sensor showing an example of the present invention, and FIGS. 2(a) to (g) are explanatory views of the manufacturing process of the method of the present invention.

The manufacturing method of the present invention will be described based on FIGS. 1 and 2.

First, as shown in FIG. 2(a), the concentration is 1014 to 1.0.
A P-type impurity layer (P+
A buried diffusion layer (10) is selectively formed with a concentration of 1016 to 1019/cm3 and a diffusion depth of about 1 to 5 μm by an ion implantation method or a thermal diffusion process.

Next, as shown in FIG. 2(b), P-type impurities are added to the P-type impurity region and other surfaces of the N-type semiconductor substrate 1 by CVD at a concentration of 1014 to 10''/(1). 3
An epitaxial layer 9 is formed with a thickness of 1 to 5 μm.

Next, as shown in Figure 2(c), N-type S
i Semiconductor substrate 1 is heat-treated to form element isolation oxide film (field oxide film) 4 having a thickness of about 1 -. Next, N type S
500-1000 SiO2 gate oxide films 5 are formed on the surface of the light receiving area and the particle CCD area of the semiconductor substrate 1 by thermal oxidation.

Furthermore, as shown in FIG. 2(d), the resist layer 1 is selectively
After forming 1, ions of phosphorus or arsenic with an impurity concentration of about 1012/c- are implanted at about 100 to 150 KeV,
The N-type impurity diffusion layer 6 forming the buried channel type charge transfer part in the particle CCD region is formed to a depth of 0.5 to 1.51 JI.
In step 11, it is formed by ion implantation and thermal diffusion.

Next, as shown in FIG. 2(e), the resist layer 11 is removed and a high concentration (approximately 3000
~5000mm thick) To form a polycrystalline silicon electrode containing an impurity, a polysilicon layer 7 containing an N-type impurity is
is formed by a CVD method or the like. Next, the polysilicon layer 7 is selectively removed using photolithography and etching techniques to form a transfer gate and a gate electrode of the CCD.

Thereafter, as shown in FIG. 2(f), phosphorus or arsenic is ion-implanted to form an N-type impurity diffusion layer 8 in the P/N light receiving diode region at a depth of 0.5 to 1.5-.

Finally, as shown in Figure 2(g), PS
A G film 12 and an AR wiring layer 13 are formed and patterned to complete the device.

After the above-mentioned manufacturing process, the P+ buried diffusion layer 10 on the N-type semiconductor substrate 1 has been subjected to several heat treatment processes, so that an autodoping phenomenon shown by A in the figure occurs in the P-type epitaxial layer 9. Figure 1 shows that this occurs and rises on the order of a few microns.

As another example, after providing a P-type impurity layer 10 on an N-type semiconductor substrate 1, an N-type epitaxial layer is formed on the entire surface.
It may be formed by the VD method, and a P well layer may be provided by ion implantation from the surface of the N type epitaxial layer.

[Effects of the Invention] As described above, according to the method for manufacturing a solid-state image sensor of the present invention, the conventional P-well layer having two types of junction depths can be replaced with a P-type impurity layer provided on an N-type semiconductor substrate. By forming 10 from the P-type epitaxial layer 9, the following effects can be achieved.

-8= (a) When a P-type epitaxial layer is used, the P-well layer can be formed without using an ion implantation process or heat treatment at high temperature for a long time, and the manufacturing process can be significantly shortened.

(b) For the same reason, a solid-state imaging device with high integration and low defects can be obtained.

(c) Due to autodoping from the P+ type impurity layer provided on the N type semiconductor substrate, a highly concentrated P type impurity layer is formed under the charge transfer section (usually referred to as V-CCD), and light reception is called smear. This has the effect of suppressing the leakage of electrons from the area.

(d) Furthermore, as the highly concentrated P-type impurity layer is brought closer to the bottom of the V-CCD, the capacitance of the V-CCD section increases and the amount of charge handled increases, so the dimensions of the V-CCD section are reduced. It can be made smaller, and as a result, the area of the light-receiving portion can be expanded, so that the light-receiving sensitivity of the element can also be improved.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a cross section of a cell of a solid-state imaging device showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of the manufacturing process of the method of this invention, and FIG. 3 is an imaging section (light-receiving cell) in a conventional solid-state imaging device. It is a cross-sectional explanatory view. In the figure, 1: N type semiconductor substrate, 2: P well layer (1
), 3: P-well layer (2), 4: oxide film for cordon isolation, 5
: Gate oxide film, 6 N-type impurity diffusion layer, 7. Polysilicon film, 8: N-type impurity diffusion layer, 9 double bi-taxial layer, 10 P-type impurity layer (P+ buried diffusion layer), t1 resist layer,] 2: PSG film, 13. This is a Δg wiring layer. 1. Indication of the case Japanese Patent Application No. 63-31875 2. Name of the invention Method for manufacturing solid-state imaging devices 3. Person making the amendment Relationship to the case Patent applicant address 1-7-12 Toranomon, Minato-ku, Tokyo
Name (029) Oki Electric Industry Co., Ltd. Representative: Nobumitsu Kosugi 4, Agent address: 4-10-3-5, Shibaura, Minato-ku, Tokyo, Column 6 of “Detailed Description of the Invention” of the specification to be amended, Amendment contents of

Claims (1)

[Claims] A method for forming a P-well layer of a solid-state imaging device, comprising: forming a P-type impurity layer on a portion of an N-type semiconductor substrate; A step of forming a P-type epitaxial layer or an N-type epitaxial layer on a semiconductor substrate, a step of providing a light receiving section and a charge transfer section on the P-type epitaxial layer, or a step of forming a P-well layer on the N-type epitaxial layer, A method for manufacturing a solid-state image sensor, comprising the steps of: providing a light receiving section and a charge transfer section on a well layer.