JPH0424872B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state image sensor, and particularly to a solid-state image sensor using a charge-coupled device.

Charge-coupled devices (hereinafter referred to as CCDs) are a new type of semiconductor functional device that can store and sequentially transfer electronic signals representing information in the form of charges. Since this charge group can be generated by an external signal voltage or incident light, it has been applied to various imaging devices, memories, and signal processing devices. Among them, solid-state image sensors using CCD are small, lightweight, low power consumption, high S/N,
Various types of imaging devices are being actively developed due to their characteristics such as high reliability.

Solid-state imaging devices using CCDs can be broadly divided into frame transfer type and interline type. Among these, the interline method has features such as a smaller chip area, less smear, and easier driving than the frame transfer method, and is becoming the mainstream among solid-state image sensors.

By the way, the biggest drawback of such solid-state image sensors is that blooming and smear development occur when strong light is incident.
Attempts have been made to form elements thereon. However, in a conventional image sensor formed on a P-well, variations in impurity distribution within the wafer surface directly appear as fixed pattern noise on the reproduced image.

FIG. 1 shows a sectional view of the main parts of a conventional image sensor formed on a P-well. In Figure 1, 1 is N
A type semiconductor substrate, 2 and 3 are P-wells formed on this substrate, 4 is a P-N junction surface, and 5 is an N-type semiconductor, which constitutes a photodiode. 6 is an N-type semiconductor region, which is a buried channel CCD (hereinafter referred to as BCCD)
Configure. 7 is a channel stopper, 8 is an oxide film, 9 is a drive electrode, 10 is a terminal for applying a pulse voltage to the electrode 9, 11 is a photodiode 5
and a transfer gate region for separating or coupling with the buried channel 6.

In FIG. 1, P-wells 2 and 3 are usually formed by ion implantation, and a reverse bias voltage is applied between them and the N-type substrate 1 during operation. Also P-
Well2 and P-well3 have different junction depths BCCD
The P-well 2 where the photodiode 6 is formed is deep, and the P-well 3 where the photodiode 5 is formed is shallow. During operation, P-well 3 is completely depleted by the reverse bias voltage, and the minimum level is P-well 3.
It is set to be deeper in the positive direction than the potential of well2. A pulse voltage having three levels of high potential, intermediate potential, and low potential is applied to the electrode 9 from a terminal 10. The signal charges photoelectrically converted in the photodiode 5 are transferred to the buried channel 6 via the transfer gate region 11 by applying the high potential to the electrode 9 during the blanking period.
is read out. Furthermore, this signal charge is transferred in the BCCD by applying a pulse having the intermediate potential or low potential to the electrode 9. The surface potential of the transfer gate region 11 when the pulse voltage is at an intermediate potential is set to be a potential smaller than the minimum potential of the P-well 3, and all excess charges generated in the photodiode region 5 are swept to the substrate 1. blooming is suppressed. By the way, the minimum potential of the P-well 3 or the potential of the trans gate region 11 is the same as that of the substrate 1, P-wells 2 and 3.
etc. depends on the impurity concentration. However, in general
In a semiconductor ingot crystal-grown by the CZ method or the like, the impurity distribution is not uniform, and the impurity concentration changes at a certain period from the center to the outer circumference. The variation in impurity concentration reaches as much as 10 to 20%. If a solid-state imaging device as described above is manufactured on a semiconductor substrate having such variations in impurity concentration, the potential of each region as described above will differ depending on the location of the device. As a result, there are disadvantages such as the charge storage capacity of each photodiode being different and the readout potential of each transfer gate being different, resulting in the disadvantage that fixed pattern noise called swirl occurs on the imaging screen.

SUMMARY OF THE INVENTION An object of the present invention is to provide a solid-state image sensor that eliminates the above-mentioned conventional drawbacks.

According to the present invention, a semiconductor layer having a conductivity type opposite to that of the semiconductor substrate is formed on a semiconductor substrate of one conductivity type, and a photodiode and a shift register are formed adjacent to the photodiode and the shift register on the semiconductor layer. In the solid-state imaging device in which a transfer gate region is formed, an epitaxial layer having the same conductivity type as the substrate is provided between the semiconductor substrate and the semiconductor layer, and an epitaxial layer having the same conductivity type as the substrate is provided. A solid-state imaging device is obtained, characterized in that a highly doped epitaxial layer having the same conductivity type as the epitaxial layer is formed.

FIG. 2 shows an embodiment of the solid-state image sensing device according to the present invention, and shows a cross-sectional view of the main parts of the device. In FIG. 2, 21 is an N-type semiconductor substrate, 22 is a semiconductor layer epitaxially grown on this substrate and has the same conductivity type as the substrate, that is, N-type, and 23 is an N-type semiconductor layer epitaxially grown on this N-type semiconductor layer. This is an N-type second semiconductor layer. The semiconductor layer 22 is doped with impurities at a higher concentration than the semiconductor layer 23.
The impurity concentration of No. 3 is selected to be approximately the same as that of the conventional semiconductor substrate 1 shown in FIG. Furthermore, in Figure 2, objects with the same numbers as in Figure 1 are numbered 1.
The same object as the figure is shown.

Next, the configuration and operation of this device will be explained. In this device, as in the case of the conventional device shown in Fig. 1, a reverse bias voltage is applied between P-wells 2 and 3 and the N-type substrate 21, and the potential of P-well 3 becomes a potential sufficient to suppress blooming. It is set. Other operations are performed in the same manner as before. Here, due to the reverse bias voltage, the N-type semiconductor layer 2
A depletion layer extends to 2 and 23. The end of this depletion layer is arranged in the N-type semiconductor layer 22 so that it remains inside the highly doped N-type semiconductor layer 22 in any state during operation.
A thickness and concentration of 2.23 was chosen. Therefore, the reverse bias voltage can be lowered compared to the case where the highly doped N-type semiconductor layer 22 is not provided. Generally, a semiconductor layer epitaxially grown on a substrate has a uniform impurity concentration distribution over the entire surface of the wafer, and as long as the thickness is at least an appropriate level, the influence of impurity concentration unevenness in the base substrate will not appear. Therefore, if the thicknesses of the semiconductor layers 22 and 23 are selected so as to provide a sufficient distance between the end of the depletion layer and the semiconductor substrate 21,
The active region of the device remains within the epitaxial layer where the impurity distribution is uniform within the wafer plane, and is not directly influenced by the substrate impurity distribution, making it possible to eliminate the swirl-like fixed pattern noise observed in the conventional device.

As described above, according to the present invention, a good solid-state image sensor without fixed pattern noise can be obtained.

In addition, in the above explanation, for convenience, an N-type substrate is used.
Although a channel device has been described, the gist of the present invention can also be applied to a P channel device using a P type substrate.

[Brief explanation of drawings]

FIG. 1 is a sectional view of the main part of a conventional image sensor formed on a P-well, and FIG. 2 is an embodiment of a solid-state image sensor according to the present invention, and shows a sectional view of the main part of the element. In the figure, 1 and 21 are N-type substrates, and 2 and 3 are P-type substrates.
-well, 4 is a junction surface between P-wells 2 and 3 and N-type substrate 1, 5 is a photodiode, 6 is a BCCD, 7 is a channel stopper, 8 is an oxide film, 9 is an electrode, 1
0 is a terminal, 11 is a transfer gate area, 22
2 is a high concentration N-type semiconductor layer epitaxially grown on the substrate 21, and 23 is an N-type semiconductor layer epitaxially grown on this semiconductor layer.

Claims (1)

[Claims] 1 A semiconductor layer having a conductivity type opposite to that of the semiconductor substrate is formed on a semiconductor substrate of one conductivity type, and a photodiode, a shift register, and a transfer transistor disposed adjacent to the photodiode and the shift register are formed on this semiconductor layer. In the solid-state imaging device in which an agate region is formed, an epitaxial layer having the same conductivity type as the substrate is provided between the semiconductor substrate and the semiconductor layer, and the epitaxial layer is provided between the epitaxial layer and the substrate. A solid-state imaging device characterized in that a highly concentrated epitaxial layer of the same conductivity type is formed.