JPH01207979A - Compound semiconductor device - Google Patents

Compound semiconductor device

Info

Publication number
JPH01207979A
JPH01207979A JP3334288A JP3334288A JPH01207979A JP H01207979 A JPH01207979 A JP H01207979A JP 3334288 A JP3334288 A JP 3334288A JP 3334288 A JP3334288 A JP 3334288A JP H01207979 A JPH01207979 A JP H01207979A
Authority
JP
Japan
Prior art keywords
layer
layers
semiconductor layer
compound semiconductor
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3334288A
Other languages
Japanese (ja)
Inventor
Akira Saito
昭 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3334288A priority Critical patent/JPH01207979A/en
Publication of JPH01207979A publication Critical patent/JPH01207979A/en
Pending legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain low contact resistance easily, by forming ohmic contact through a highly concentrated layer on a two dimensional electronic gas region. CONSTITUTION:n<+> type GaAs layers 6a and 6b are formed between source and drain electrodes 1 and 3 as well as non-doped GaAs layer 5 respectively. A two dimensional gas region 7 is in existence between the n<+> type GaAs layers 6a and 6b of 0.5mum thickness. As the above layers 6a and 6b are formed as the third semiconductor layers on the non-doped GaAs layer 5 which is the first semiconductor layer, ohmic contact having low contact resistance is formed easily on the surface of the layers 6a and 6b. Resistance between the n<+> type GaAs layers and the two dimensional electronic gas region 7 is so small that a compound semiconductor having low resistance between the gate and source electrodes is obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は化合物半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a compound semiconductor device.

〔従来の技術〕[Conventional technology]

第2図は従来の化合物半導体装置の一例の断面図である
。
FIG. 2 is a cross-sectional view of an example of a conventional compound semiconductor device.

化合物半導体装置は、半絶縁性GaAs層の上に第1の
半導体層である非ドープGaAs層5と、第2の半導体
層であるA I!(1−x) G a x層4を重ねて
形成し、その表面にゲート電極2を挟んでソース電極1
及びドレイン電極3を設けて構成さ4の界面にはへテロ
接合が形成され、非ドープGaAs層5の表面下の点線
内に移動度の高い二次元電子ガス領域7が形成される。
The compound semiconductor device includes an undoped GaAs layer 5 which is a first semiconductor layer on a semi-insulating GaAs layer, and an A I! layer which is a second semiconductor layer. (1-x) G a
A heterojunction is formed at the interface between the electrode 4 and the drain electrode 3, and a two-dimensional electron gas region 7 with high mobility is formed within the dotted line below the surface of the undoped GaAs layer 5.

ソース及びドレイン電極1及び3の下に低抵抗のオーミ
ック層を形成するため、電子供給層であるA13・−・
・GM・層4の表面にオーミ・2り金属を蒸着し、熱処
理によって低抵抗合金層を形成していた。
In order to form a low resistance ohmic layer under the source and drain electrodes 1 and 3, the electron supply layer A13...
・Ohmi-2 metal was vapor-deposited on the surface of GM layer 4, and a low-resistance alloy layer was formed by heat treatment.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した化合物半導体装置は、電子供給層の表面にオー
ミックコンタクトを形成することは必すしも容易でなく
、安定して低コンタクト抵抗か得られないという問題が
あった。
The above-described compound semiconductor device has a problem in that it is not necessarily easy to form an ohmic contact on the surface of the electron supply layer, and a stable low contact resistance cannot be obtained.

種々の電子供給層の材料の中から二次元電子ガスの移動
度、電子濃度等について最適なものを選んだとしても、
上述のオーミックコンタク1〜か形成できない場合もあ
り、任意の結晶が電子供給層として使用できるとは限ら
ないという欠点も有している。
Even if one chooses the best material for the two-dimensional electron gas mobility, electron concentration, etc. from various materials for the electron supply layer,
There are also cases where the above-mentioned ohmic contacts 1 to 1 cannot be formed, and there is also the drawback that any crystal can not always be used as the electron supply layer.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の化合物半導体装置は、第1の半導体層の表面に
該第1の半導体層と電子親和力の異なる第2の半導体層
を形成し、前記二つの半導体層の界面に高移動度の二次
元電子ガス領域を有してヘテロ接合を形成し、前記第2
の半導体層の表面にゲート電極を有する化合物半導体装
置において、前記ゲート電極を挟んて設けられたソース
及びドレイン電極と前記第1の半導体層とそれぞれとの
間に該第1の半導体層よりも高不純物濃度の第3の半導
体層を設けて構成されている。
In the compound semiconductor device of the present invention, a second semiconductor layer having a different electron affinity from the first semiconductor layer is formed on the surface of the first semiconductor layer, and a high mobility two-dimensional forming a heterojunction with an electron gas region;
In a compound semiconductor device having a gate electrode on the surface of a semiconductor layer, a height higher than that of the first semiconductor layer is provided between the source and drain electrodes provided with the gate electrode in between and the first semiconductor layer. A third semiconductor layer having an impurity concentration is provided.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.

化合物半導体装置は、ソース電極1及びドレイン電極3
と非ドープGaAs層5との間にそれぞれn+GaAs
層6a、6bを設けた点か異る以外は第2図の従来の化
合物半導体装置の同一である。
The compound semiconductor device has a source electrode 1 and a drain electrode 3.
and the undoped GaAs layer 5, respectively.
This device is the same as the conventional compound semiconductor device shown in FIG. 2 except that layers 6a and 6b are provided.

二次元電子ガス領域7は005μmの厚さの二つのn+
GaAs層6a、6bの間に存在している。第1の半導
体層である非ドープGaAs層5の表面に第3の半導体
層としてn+GaAs層6を形成しているので、その表
面には容易に低コンタクト抵抗のオーミックを形成でき
る。
The two-dimensional electron gas region 7 has two n+
It exists between the GaAs layers 6a and 6b. Since the n+ GaAs layer 6 is formed as the third semiconductor layer on the surface of the undoped GaAs layer 5 as the first semiconductor layer, an ohmic contact with low contact resistance can be easily formed on the surface.

n+GaAs層と二次元電子カス領域7間の抵抗は小さ
いので、ゲート・ソース間抵抗の低い化合物半導体が得
られる。
Since the resistance between the n+GaAs layer and the two-dimensional electron waste region 7 is small, a compound semiconductor with low gate-source resistance can be obtained.

なお、n4GaAs層6a、6bは非ドープGaAs層
5を貫いてもよい。
Note that the n4GaAs layers 6a and 6b may penetrate the undoped GaAs layer 5.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、二次元電子ガス領域に高
濃度層を介して、オーミックコンタクトを形成するのて
、容易に低コンタクト抵抗が得られる。
As explained above, in the present invention, a low contact resistance can be easily obtained by forming an ohmic contact in a two-dimensional electron gas region via a high concentration layer.

従って、ソース寄生抵抗の小さいヘテロ接合の化合物半
導体装置が容易に得られる。
Therefore, a heterojunction compound semiconductor device with low source parasitic resistance can be easily obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の断面図、第2図は従来の化
合物半導体装置の一例の断面図である。 1・・・ソース電極、2・・・ゲート電極、3・・・ド
レイン電極、4・・・A I!(s−x) G a x
 A s層、5・・・非ドープGaAs層、6−・−n
+GaAs層、7・・二次元カス領域。
FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of an example of a conventional compound semiconductor device. 1... Source electrode, 2... Gate electrode, 3... Drain electrode, 4... A I! (s-x) G a x
As layer, 5... undoped GaAs layer, 6--n
+GaAs layer, 7... two-dimensional waste region.

Claims (1)

【特許請求の範囲】[Claims]  第1の半導体層の表面に該第1の半導体層と電子親和
力の異なる第2の半導体層を形成し、前記二つの半導体
層の界面に高移動度の二次元電子ガス領域を有してヘテ
ロ接合を形成し、前記第2の半導体層の表面にゲート電
極を有する化合物半導体装置において、前記ゲート電極
を挟んで設けられたソース及びドレイン電極と前記第1
の半導体層とそれぞれとの間に該第1の半導体層よりも
高不純物濃度の第3の半導体層を設けたことを特徴とす
る化合物半導体装置。
A second semiconductor layer having a different electron affinity from the first semiconductor layer is formed on the surface of the first semiconductor layer, and a two-dimensional electron gas region with high mobility is formed at the interface of the two semiconductor layers to form a heterogeneous semiconductor layer. In a compound semiconductor device that forms a junction and has a gate electrode on the surface of the second semiconductor layer, the source and drain electrodes provided with the gate electrode sandwiched therebetween and the first
A compound semiconductor device characterized in that a third semiconductor layer having a higher impurity concentration than the first semiconductor layer is provided between each of the semiconductor layers.
JP3334288A 1988-02-15 1988-02-15 Compound semiconductor device Pending JPH01207979A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3334288A JPH01207979A (en) 1988-02-15 1988-02-15 Compound semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3334288A JPH01207979A (en) 1988-02-15 1988-02-15 Compound semiconductor device

Publications (1)

Publication Number Publication Date
JPH01207979A true JPH01207979A (en) 1989-08-21

Family

ID=12383892

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3334288A Pending JPH01207979A (en) 1988-02-15 1988-02-15 Compound semiconductor device

Country Status (1)

Country Link
JP (1) JPH01207979A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06163600A (en) * 1992-11-26 1994-06-10 Nec Corp Field-effect transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06163600A (en) * 1992-11-26 1994-06-10 Nec Corp Field-effect transistor

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