JPH01208021A - Integrated logic circuit - Google Patents
Integrated logic circuitInfo
- Publication number
- JPH01208021A JPH01208021A JP63033077A JP3307788A JPH01208021A JP H01208021 A JPH01208021 A JP H01208021A JP 63033077 A JP63033077 A JP 63033077A JP 3307788 A JP3307788 A JP 3307788A JP H01208021 A JPH01208021 A JP H01208021A
- Authority
- JP
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- Prior art keywords
- circuit
- voltage side
- low voltage
- logic circuit
- vss
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
ＣＭＯ５系集積論集積論理回路端子にその開放時の論理
動作の不確定を避けるため設けられるプルダウン抵抗の
回路に関し、
プルダウン抵抗の回路における電力消費を無（してＣＭ
Ｏ３系集積論集積論理回路費電力性を保つことを目的と
し、
プルダウン抵抗と電源の低圧側（ＶＳＳ）の間にスイッ
チを設け、該スイッチをＣＭＯＳ論理回路の初段回路の
出力電位により制御して、回路に入力する２値信号が高
レベルＨの場合に、プルダウン抵抗と電源の低圧側ＶＳ
Ｓの接続をオフとする構成としたものである。[Detailed Description of the Invention] [Summary] Regarding a pull-down resistor circuit provided in a CMO5 integrated logic circuit terminal in order to avoid uncertainty in logic operation when the terminal is open, the present invention relates to a pull-down resistor circuit that eliminates power consumption in the pull-down resistor circuit. CM
In order to maintain the O3 system integrated logic circuit cost and power efficiency, a switch is provided between the pull-down resistor and the low voltage side (VSS) of the power supply, and this switch is controlled by the output potential of the first stage circuit of the CMOS logic circuit. , when the binary signal input to the circuit is at high level H, the pull-down resistor and the low voltage side of the power supply VS
The configuration is such that the connection of S is turned off.
本発明はＣＭＯ３系集積論集積論理回路、特に該回路の
入力端子にその開放時の論理動作の不確定を避けるため
設けられる所謂プルダウン抵抗の回路に関する。The present invention relates to a CMO3 integrated logic circuit, and particularly to a so-called pull-down resistor circuit provided at an input terminal of the circuit to avoid uncertainty in logic operation when the input terminal is open.
ＣＭＯＳ系論理回路としては、その特徴である低消費電
力性を失わないようにするため、前記プルダウン抵抗の
回路における電力消費が無いことが望まれている。As a CMOS logic circuit, it is desired that the pull-down resistor circuit consume no power so as not to lose its characteristic low power consumption.
従来のＣＭＯＳ系集積論理回路の一例を第３図に示す。 An example of a conventional CMOS integrated logic circuit is shown in FIG.
同図の論理回路は、正電源ＶＤＤと負電源ｖＳＳＯ間に
、Ｐチャネル上ＦＥＴ １１４のドレインＤＩとＮチャ
ネルＦＥ７１２八〇ドレインＤ２とを１妾続して縦続し
所謂相補接続したインバータＩＡと、ＰチャネルＦＥＴ
４１ＡとＮチャネルＦＥＴ ４２Ａを同様に相補接続
したインバータ４八からなる２段構成のＣＭＯＳ系イン
バータ回路であって、該回路の信号の入力端子であるイ
ンバータ１のＰチャネルＦＥＴ ＩＩＡとＮチャネルＦ
ＥＴ １２Ａの両ゲートＧｌ、Ｇ２の接続点ｔ１に２値
信号Ｌ／Ｈが入力すると、インバータＩＡのＰチャネル
上ＦＥＴ １１八がＯＮ／ Ｏｆ’ＦとなりＮチャネ
ルＦＥ７１２Δが０ＦＦ１０Ｎとなって、入力信号の符
号Ｌ／Ｈを符号＋１／Ｌに反転してインバータ４Ａへ出
力し、又インバータ４Ａは、そのＰチャネルＦＥＴ ４
１Ａが０ＦＦ１０Ｎ。The logic circuit in the figure includes an inverter IA in which the drain DI of a P-channel upper FET 114 and the drain D2 of an N-channel FE712 are cascaded and so-called complementary connected between a positive power supply VDD and a negative power supply vSSO; P channel FET
This is a two-stage CMOS inverter circuit consisting of 48 inverters in which 41A and N-channel FET 42A are similarly connected in a complementary manner.
When the binary signal L/H is input to the connection point t1 between both gates Gl and G2 of ET 12A, the P-channel upper FET 118 of the inverter IA turns ON/Off'F, and the N-channel FE712Δ becomes 0FF10N, and the input signal The sign L/H of is inverted to sign +1/L and output to the inverter 4A, and the inverter 4A inverts the P channel FET 4.
1A is 0FF10N.
ＮチャネルＦＥＴ ４２ Ａが０Ｎ１０ＦＦとなってそ
の入力符号Ｈ／Ｌを符号反転して出力端子ｔ２から２値
信号Ｌ／１１を出力する。The N-channel FET 42A becomes 0N10FF, inverts the sign of its input sign H/L, and outputs a binary signal L/11 from the output terminal t2.
そして初段回路のインバータＩＡの入力端子ｔ１と負電
源ＶＳＳＯ間に抵抗２八を所謂プルダウン抵抗として設
けて電源の負電源ＶＳＳに接続し、入力端子ｔ１の開放
時の回路の論理動作の不確定を避ける構成となっている
。Then, a resistor 28 is provided as a so-called pull-down resistor between the input terminal t1 of the inverter IA of the first stage circuit and the negative power supply VSSO, and is connected to the negative power supply VSS of the power supply, thereby eliminating uncertainty in the logic operation of the circuit when the input terminal t1 is open. It is configured to avoid this.
従来のＣＭＯＳ系集積論理回路は、上述の如く、Ｐチャ
ネルＦＥＴ ＩＩＡとＮチャネルＦＥＴ １２Ａを相補
接続した初段回路ＩＡの入力端子ｔ１と負電源ＶＳＳの
間にプルダウン抵抗２Ａを設け、該入力端子ｔ１の開放
時の回路の論理動作の不確定を避ける構成となっている
ので、該初段回路ＩＡの入力端子ｔｌに２値入力の符号
Ｈが入力する時は、プルダウン抵抗２Ａに電流が流れて
該プルダウン抵抗２Ａで電力が消費され、ＣＭＯＳ系集
積論理回路の特徴である低消費電力性が失われるという
問題がある。As described above, in the conventional CMOS integrated logic circuit, a pull-down resistor 2A is provided between the input terminal t1 of the first stage circuit IA, which has the P-channel FET IIA and the N-channel FET 12A connected in a complementary manner, and the negative power supply VSS, and the pull-down resistor 2A is provided between the input terminal t1 and the negative power supply VSS. The structure is designed to avoid uncertainty in the logical operation of the circuit when the circuit is open, so when the binary input sign H is input to the input terminal tl of the first stage circuit IA, a current flows through the pull-down resistor 2A and the There is a problem in that power is consumed by the pull-down resistor of 2 A, and the low power consumption characteristic of CMOS integrated logic circuits is lost.
この問題は、ＰチャネルＦＥＴ １１ とＮチャネルＦ
ＥＴ １２を相補接続するＣＭＯ３論理回路の入力端子
ｔ１にスイッチ４を設け、２値入力の信号Ｈが入力する
時、該回路の初段回路の出力の符号反転した信号りによ
り駆動され、プルダウン抵抗３と負電源ＶＳＳの接続を
切断するようにした本発明の構成によって解決される。This problem is solved by P-channel FET 11 and N-channel FET 11
A switch 4 is provided at the input terminal t1 of the CMO3 logic circuit that connects the ET 12 in a complementary manner, and when a binary input signal H is input, it is driven by a signal with the sign inverted from the output of the first stage circuit of the circuit, and the pull-down resistor 3 This problem is solved by the configuration of the present invention, which disconnects the negative power supply VSS.
本発明の集積論理回路の構成を示す第１図の原理図にお
いて、
■は、ＰチャネルＦＥＴ １１とＮチャネルＦＥＴ １
２が相補接続され電源の高圧側ＶＤＤと低圧側ＶＳＳの
間に相補接続され入力信号の符号を反転するＣＭＯ５論
理回路の初段回路、
２は、初段回路１の入力端子ｔ１に接続されスイッチ３
を介して電源の低圧側ｖＳＳに接続されるプルダウン抵
抗、
３は、プルダウン抵抗２と電源の低圧側ｖＳＳの接続を
、初段回路１の出力電位により制御されオン／オフする
スイッチであって、
スイッチ３が、入力端子ｔ１に入力する２値信号が高レ
ベル１１の場合、即ち初段回路１の出力電位が低レベル
Ｌのとき、プルダウン抵抗２と電源の低圧側ｖＳＳとの
接続をオフにする構成とする。In the principle diagram of FIG. 1 showing the configuration of the integrated logic circuit of the present invention, (2) indicates a P-channel FET 11 and an N-channel FET 1.
2 is a first stage circuit of a CMO5 logic circuit which is complementary connected between the high voltage side VDD and the low voltage side VSS of the power supply and inverts the sign of the input signal; 2 is connected to the input terminal t1 of the first stage circuit 1 and is a switch 3;
The pull-down resistor 3 is connected to the low-voltage side vSS of the power supply via the pull-down resistor 2, and 3 is a switch that turns on/off the connection between the pull-down resistor 2 and the low-voltage side vSS of the power supply, controlled by the output potential of the first stage circuit 1. 3 is a configuration in which the connection between the pull-down resistor 2 and the low voltage side vSS of the power supply is turned off when the binary signal input to the input terminal t1 is at high level 11, that is, when the output potential of the first stage circuit 1 is at the low level L. shall be.
ＣＭＯ５論理回路の初段回路１は、ＰチャネルＦＥ７１
１とＮチャネルＦＥＴ １２が電源の高圧側ＶＤＤと低
圧側ＶＳＳＯ間に相補接続され、該回路１の信号の入力
端子であるＰチャネルＦＥＴ １１とＮチャネルＩ？Ｅ
Ｔ １２０両ゲートの接続点ｔ１に２値の入力信号Ｌ／
Ｈが入力すると、ＰチャネルＦＥＴ １１が０Ｎ１０Ｆ
ＦとなりＮチャネルＦＥＴ １２が０ＦＦ１０Ｎとなっ
て入力信号の符号Ｌ／１１を符号Ｈ／Ｌに反転して出力
端子ｔａから出力し、２値の入力符号を反転するインバ
ータを形成する。The first stage circuit 1 of the CMO5 logic circuit is a P-channel FE71.
1 and N channel FET 12 are complementary connected between the high voltage side VDD and low voltage side VSSO of the power supply, and the P channel FET 11 and N channel I? E
T 120 A binary input signal L/ is connected to the connection point t1 of both gates.
When H is input, P channel FET 11 becomes 0N10F
F, the N-channel FET 12 becomes 0FF10N, the sign L/11 of the input signal is inverted to the sign H/L, and the signal is output from the output terminal ta, forming an inverter that inverts the binary input sign.
プルダウン抵抗２は、初段回路１の入力端子ｔ１にその
一方の端が接続され他方の端がスイッチ３を介して電源
の低圧側ＶＳＳに接続され、スイッチ３が、初段回路１
の出力端子ｔａの電位Ｌ／Ｈによりオン／オフ制御され
るので、入力端子ｔｌに入力する２値信号が符号りの時
は出力端子ｔａの電位が１１となるのでオンとなってプ
ルダウン抵抗２と電源の低圧側ＶＳＳが接続されるが、
抵抗の両端に電位差がない為に電力は消費されない。ま
た、入力端子ｔ１に入力する２値信号が符号１１になる
と初段回路１の出力端子ｔａの電位がＬとなってプルダ
ウン抵抗２と電源の低圧側ＶＳＳの接続が切断される。The pull-down resistor 2 has one end connected to the input terminal t1 of the first stage circuit 1 and the other end connected to the low voltage side VSS of the power supply via the switch 3.
Since the on/off control is controlled by the potential L/H of the output terminal ta of and the low voltage side VSS of the power supply are connected,
Since there is no potential difference across the resistor, no power is consumed. Further, when the binary signal input to the input terminal t1 becomes 11, the potential of the output terminal ta of the first stage circuit 1 becomes L, and the connection between the pull-down resistor 2 and the low voltage side VSS of the power supply is disconnected.
従って本発明の集積論理回路は、回路に入力する２値信
号が符号１１のときプルダウン抵抗２には電流が流れず
電力が消費されないので、ＣＭＯＳ論理回路の特徴の低
消費電力性は保持されて問題は解決される。Therefore, in the integrated logic circuit of the present invention, when the binary signal input to the circuit is 11, no current flows through the pull-down resistor 2 and no power is consumed, so that the low power consumption characteristic of the CMOS logic circuit is maintained. The problem will be resolved.
また、入力の開放時には、−時、出力端子ｔａが中間電
位になり、スイッチがほぼオンになる。このため、人力
は符号り側に傾く。Further, when the input is open, the output terminal ta becomes an intermediate potential at - time, and the switch is almost turned on. For this reason, human power leans toward the positive side.
第２図は本発明の実施例の集積論理回路の構成を示す回
路図である。第２図の回路図において、ＣＭＯＳ論理回
路の初段回路Ｉは、ＰチャネルＦＥＴ１１とＮチャネル
ＰＥ７１２が相補接続されたインバータ１であって、次
段のＰチャネルＦＥＴ ４１とＮチャネル ＦＥＴ ４
２が相補接続されたインバータ２と２段構成のＣＭＯＳ
インバータを構成する。FIG. 2 is a circuit diagram showing the configuration of an integrated logic circuit according to an embodiment of the present invention. In the circuit diagram of FIG. 2, the first stage circuit I of the CMOS logic circuit is an inverter 1 in which a P channel FET 11 and an N channel PE 712 are connected in a complementary manner, and the next stage P channel FET 41 and N channel FET 4
Inverter 2 and two-stage CMOS are connected complementary to each other.
Configure the inverter.
本実施例のプルダウン抵抗２は、抵抗器２１で構成され
、該抵抗器２１の一端が前記インバータ１のＦＥＴ １
１とＰＥＴ １２のゲートＧｌ、Ｇ２の接続点である入
力端子ｔ１に接続され、他端がスイッチ３を介して電源
の低圧側ｖＳＳに接続される。The pull-down resistor 2 of this embodiment is composed of a resistor 21, and one end of the resistor 21 is connected to the FET 1 of the inverter 1.
1 and the gates Gl and G2 of the PET 12, and the other end thereof is connected to the low voltage side vSS of the power supply via the switch 3.
本実施例のスイッチ３は、ＮチャネルＦＥＴ ３１で構
成され、該ＰＥＴ ３１のゲートＧ３が、インバータ１
のＦＥＴ １１ とＦＥＴ １２のドレインＤＩ、Ｄ２
の接続点である出力端子ｔａと接続され、該ＦＩＥＴ
３１のドレインＤ３がプルダウン抵抗２の抵抗２１に接
続され、該ＮチャネルｒｉＥＴ ３１のソースＳ３がそ
のベースＢと共に電源の低圧側ＶＳＳに接続される。The switch 3 of this embodiment is composed of an N-channel FET 31, and the gate G3 of the PET 31 is connected to the inverter 1.
Drain DI, D2 of FET 11 and FET 12
is connected to the output terminal ta, which is the connection point of the FIET
The drain D3 of the N-channel riET 31 is connected to the resistor 21 of the pull-down resistor 2, and the source S3 of the N-channel riET 31 is connected together with its base B to the low voltage side VSS of the power supply.
スイッチ３ＯＮチヤネルＦＥ７３１は、初段回路１であ
るインバータ１の出力端子ｔａの電位Ｌ／Ｈによりドレ
インＤ３とソースＳ３の間がオン／オフされるので、イ
ンバータ１の入力端子ｔ１に入力する２値信号が符号１
７の時は出力端子ｔａの電位がｌ（となるのでオンとな
ってプルダウン抵抗２と電源の低圧側ＶＳＳを接続する
が、入力端子ｔｌに入力する２値信号が符号Ｈになると
初段回路１の出力端子ｔａの電位がＬとなるので、Ｎチ
ャネルＦＥＴ ３１のドレインＤ３とソースＳ３の間が
オフされ、プルダウン抵抗２と電源の低圧側ＶＳＳの接
続が切断される。The switch 3 ON channel FE731 is turned on/off between the drain D3 and the source S3 by the potential L/H of the output terminal ta of the inverter 1 which is the first stage circuit 1, so the binary signal input to the input terminal t1 of the inverter 1 is switched on/off. is code 1
7, the potential of the output terminal ta becomes l(, so it turns on and connects the pull-down resistor 2 and the low voltage side VSS of the power supply. However, when the binary signal input to the input terminal tl becomes sign H, the first stage circuit 1 Since the potential of the output terminal ta becomes L, the connection between the drain D3 and the source S3 of the N-channel FET 31 is turned off, and the connection between the pull-down resistor 2 and the low voltage side VSS of the power supply is cut off.
従って本実施例の集積論理回路は、インバータ１に入力
する２値信号が符号１１の時にプルダウン抵抗２には電
流が流れず電力が消費されないのでＣＭＯＳ論理回路の
特徴の低消費電力性は保持されて問題は無い。Therefore, in the integrated logic circuit of this embodiment, when the binary signal input to the inverter 1 is 11, no current flows through the pull-down resistor 2 and no power is consumed, so that the low power consumption characteristic of the CMOS logic circuit is maintained. There is no problem.
以上説明した如く、本発明のＣＭＯ５集積論理回路は、
プルダウンの機能を果たしつつ、回路に入力する２値信
号の符号がＨの時に、プルダウン抵抗に電流を流さず電
力を消費しないので、ＣＭＯＳ論理回路の特徴の低消費
電力性を保持できるという効果が得られる。As explained above, the CMO5 integrated logic circuit of the present invention is
While performing the pull-down function, when the sign of the binary signal input to the circuit is H, no current flows through the pull-down resistor and no power is consumed, so the low power consumption characteristic of CMOS logic circuits can be maintained. can get.
第１図は本発明の集積論理回路の構成を示す原理図、
第２図は本発明の実施例の集積論理回路の構成を示す回
路図、
第３図は従来の集積論理回路の回路図である。
図において、
ｌはＣＭＯＳ論理回路の初段回路でありインバータ、１
１はＰチャネルＦＥＴ、
１２はＮチャネルＦＥＴ。
２は プルダウン抵抗、
３は スイ・ノチ、
３１はＮチャネルＦＥＴ。
４は インバータである。
電源高三側
悸搬芒明す集ネ責論理回語の溝承渣示マ原工里図草 １
図
電源（高圧便１）
電源（１″医圧倒）
草 ２ 口Figure 1 is a principle diagram showing the configuration of an integrated logic circuit according to the present invention, Figure 2 is a circuit diagram showing the configuration of an integrated logic circuit according to an embodiment of the present invention, and Figure 3 is a circuit diagram of a conventional integrated logic circuit. be. In the figure, l is the first stage circuit of the CMOS logic circuit, and is an inverter, 1
1 is a P-channel FET, 12 is an N-channel FET. 2 is a pull-down resistor, 3 is a sui-nochi, and 31 is an N-channel FET. 4 is an inverter. Power source high school three side palpitation, collection of logic loops, grooves, illustrations of Hara factory map 1
Figure power supply (high pressure stool 1) power supply (1″ medical overwhelming) grass 2 mouths
Claims (1)
を電源の高圧側（ＶＤＤ）と低圧側（ＶＳＳ）の間に相
補接続して２値信号入力の符号を反転するＣＭＯＳ論理
回路の初段回路（１）の入力端子（ｔ１）に抵抗（２）
を接続して電源の低圧側（ＶＳＳ）と接続する集積論理
回路において、 該抵抗（２）と電源の低圧側（ＶＳＳ）の間に前記初段
回路（１）の出力電位により制御されるスイッチ（３）
を設け、 該初段回路（１）の入力端子（ｔ１）に入力する２値信
号が高レベル（Ｈ）の場合、スイッチ（３）が抵抗（２
）と電源の低圧側（ＶＳＳ）との接続をオフにすること
を特徴とする集積論理回路。[Claims] P-channel FET (11) and N-channel FET (12)
A resistor (2) is connected to the input terminal (t1) of the first stage circuit (1) of a CMOS logic circuit that is complementary connected between the high voltage side (VDD) and low voltage side (VSS) of the power supply to invert the sign of the binary signal input.
In the integrated logic circuit connected to the low voltage side (VSS) of the power supply by connecting the resistor (2) and the low voltage side (VSS) of the power supply, a switch ( 3)
is provided, and when the binary signal input to the input terminal (t1) of the first stage circuit (1) is at a high level (H), the switch (3) is connected to the resistor (2).
) and the low voltage side (VSS) of the power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63033077A JPH01208021A (en) | 1988-02-16 | 1988-02-16 | Integrated logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63033077A JPH01208021A (en) | 1988-02-16 | 1988-02-16 | Integrated logic circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01208021A true JPH01208021A (en) | 1989-08-22 |
Family
ID=12376648
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63033077A Pending JPH01208021A (en) | 1988-02-16 | 1988-02-16 | Integrated logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01208021A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013183616A (en) * | 2012-03-05 | 2013-09-12 | Toshiba Corp | Operation control circuit, dc-dc converter control circuit and dc-dc converter |
-
1988
- 1988-02-16 JP JP63033077A patent/JPH01208021A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013183616A (en) * | 2012-03-05 | 2013-09-12 | Toshiba Corp | Operation control circuit, dc-dc converter control circuit and dc-dc converter |
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