JPH01208933A - Loop type communication system - Google Patents

Abstract

PURPOSE:To evade the loss of a data by providing a memory having a capacity for 2-frame, a detection means detecting thee reduction in the number of frames and a memory control means to a control station and driving the memory by the capacity for 2 frames when the reduction in the frame number is detected. CONSTITUTION:The delay in the final one bit X in a data field 31 from the transmission of a frame with X=0 to the reception in a transmission line is compared with a setting comparison value at a comparator 45. When a delay value represented by a delay counter 41 is larger than the setting comparison value of a comparison value storage section 43, the memory 21a is driven by a capacity by one frame. When the delay value is smaller than the output of the storage section 43, the delay on the transmission line is reduced and it is possible to be more or less near an integral number of multiple of one frame. Thus, the memory 21a is driven by the capacity by 2 frames. Thus, even when loop one circulation time is close to an integral number of multiple of the frame period, the danger of the loss of data is less and the communication with high reliability is attained.

Description

[Detailed description of the invention] [Object of the invention J (Industrial application field) TECHNICAL FIELD The present invention relates to a loop communication system.

(Prior Art) Conventionally, there is a loop communication system as shown in FIG.

As shown in the figure, this loop communication system connects a control station 1 and stations 3a, 3b, and 3c through a transmission line 5. Frames are circulated through this transmission path 5 to perform communication between each station.

FIG. 6 is a block diagram showing the configuration of the control station 1. As shown in the figure, the control station 1 includes a reception shift register 7, a frame header detection section (FH detection section) 9, a reception counter 11, an oscillator 13, a transmission counter 15, a transmission shift register 17, a memory control section 19, and a frame header generation section (FH generation section) 23.

FIG. 7 is a format diagram of the frame 25 circulating on the transmission line 5.

As shown in the figure, this frame 25 consists of a plurality of slots 27. The first slot is the frame header 29. The slot 27 consists of an 8-bit data field 31 and a 2-bit control field 33. Frame header 29 indicates the beginning of the frame. The data field 31 is loaded with data to be communicated. The control field 33 is loaded with control information.

In FIG. 6, reception shift register 7 receives reception data and a reception clock, converts the serial type reception data into parallel type data, and outputs the parallel type data to FH detection section 9 and memory 21. The FH detection unit 9 detects whether the data sent from the reception shift register 7 matches a predetermined frame header pattern, and if it matches, the reception counter 11 and the FH generation unit 23
send a signal to. The reception counter 11 starts counting when a signal is sent from the FH detection section 9, and sends the count value to the memory control section 19. The memory control unit 19 gives the sent count value to the memory 21 as an address of the memory 21. The memory 21 writes data sent from the reception shift register 7 in each slot in accordance with the address sent from the memory control section 19. Oscillator 13 is 32 MHz
This signal is generated as a transmission clock and is sent to the transmission counter 15. Transmission counter 15 oscillates 2S
13, and sends the count value to the memory control unit 19, the transmission shift register 17, and the FH generation unit 2.
Send to 3. The memory control unit 19 provides the count value sent from the transmission counter 15 as an address of the memory 21. The memory 21 sends the stored data for one slot to the transmission shift register 17 in accordance with the read address sent from the memory control unit 19. The transmission shift register 17 converts the data sent from the memory 21 into serial type data and sends it to the transmission line 5 as transmission data. At this time, a frame header generated by the FH generating section 23 is added to the beginning of the frame.

In such a loop communication system, as described above, a slot is made up of an 8-bit data field 31 and a 2-bit control field 33 to form a 400-slot frame, which is looped around every 125 μs.

As shown in FIG. 8, when one frame is circulating on the transmission line 5, the remaining 125 μs frame after subtracting the part circulating on the loop is held in the memory 21. do.

In the case shown in FIG. 9, two frames are circulating on the transmission line 5, and the remainder after subtracting the part circulating on the loop from the 2X 125 μs frames is stored in the memory 21. to hold.

In either case of FIG. 8 or FIG. 9, it is sufficient for the memory 21 to have a capacity for one frame.

However, in conventional loop communication systems, when the loop time is close to an integral multiple of the frame period,
The number of frames in the loop may change frequently due to station bypasses, temperature changes in the transmission path, etc. In this case, for example, when three frames are circulating on the transmission path 5, the number of frames circulating before reaching the partner station becomes two frames, and data for one frame is lost.

(Problem 8 to be Solved by the Invention) As described above, in the conventional loop type communication system, there has been a problem that frames are lost when the loop time is close to an integral multiple of the frame period.

The present invention has been made in view of these problems, and provides a loop communication system that allows highly reliable communication without the risk of data loss even when the loop time is close to an integral multiple of the frame period. It is about providing.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention connects a control station and a plurality of stations in a loop via a transmission path, and transmits frames to the transmission path. In a loop type communication system in which communication is performed between each station by circulating the transmission line, and the number of frames circulated on the transmission line can be varied, the control station includes a memory having a capacity for two frames, and a frame on the transmission line. a detecting means for detecting a decrease in the number of frames circulating on the transmission path; and a detecting means for detecting a decrease in the number of frames circulating on the transmission path; and a detecting means for driving the memory with a capacity for one frame under normal conditions; The memory controller is characterized in that it is provided with a memory control means for driving the memory with a capacity corresponding to that of the memory.

(Function) The memory of the control station has a capacity for two frames, and normally this memory is driven with a capacity for one frame, and when the detection means detects that the number of frames on the transmission path has decreased, this memory is activated. Data loss is avoided by driving with a capacity for two frames.

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings.

The loop communication system according to this embodiment has a configuration similar to that shown in FIG.

That is, FIG. 1 is a block diagram showing the configuration of the control station 1 in this embodiment, and elements that perform the same functions as those in the conventional example shown in FIG. 6 are given the same numbers to avoid redundant explanation.

As shown in FIG. 1, this embodiment newly includes an initial value control section 37, 39, a delay counter 41, and a comparison value storage section 4.
3. A comparator 45 and a divider 47 are provided. - Furthermore, a memory control means 49 is constituted by the reception counter 11, the transmission counter 15, the memory control section 19, and the initial value control section 37.39. Further, a delay counter 41, a comparison value storage section 4
3, the comparator 45 and the divider 47 constitute the detection means 51.

The initial value control section 37 provides an initial value to the reception counter 11 according to the output of the comparator 45. In other words, the memory 21a is
When driving with frame capacity, receive counter 11
When the count value of the reception counter 11 reaches "400°," the count is increased from "l".On the other hand, when the memory 21a is driven with a capacity for two frames, when the count value of the reception counter 11 reaches "800", the count is increased from "l". The initial value control section 39 gives the initial value of the transmission counter 15 in accordance with the output of the comparator 45. That is, when the memory 21a is driven with a capacity for one frame, the transmission counter 15 When the value of the transmission counter 15 reaches 400m, the count is incremented from 1m, and when the memory 21a is driven with a capacity for two frames, the count is incremented from 1 when the value of the transmission counter 15 reaches 800.

The delay counter 41 measures the amount of delay from transmitting a certain frame to receiving that frame.
The time from when a frame header is generated by the pattern generator 23 to when the frame header is detected by the FH detector 9 is counted, held, and then output to the comparator 45.

The memory 21a can store data for two frames, as shown in FIG. That is, it has a data capacity of 800 slots.

Next, the operation of this embodiment will be explained.

FIG. 3 shows the frame format in this embodiment, and is the frame format when one frame circulates on the transmission path.

The first slot is an all 1m frame header FH. This is followed by the second slot to the 400th slot. Each slot has an 8-bit data field 3
It consists of a control field 33 of 1 and 2 bits. The last 1 bit X of the data field 31 is "0" for only one frame when there are multiple frames on the transmission path, and "1" for the remaining frames, and when a single frame is circulating, becomes “0”. Also, control field 3
The first 1 bit of 3 becomes the complement of X. The comparison value storage unit 43 stores setting values to be compared, and the number of slots in one frame is stored as an initial value.

A comparator 45 connects the output of the delay counter 41 and the comparison value storage section 4.
3, and when the output value of the delay counter 41 is smaller than the output value of the comparison value storage section 43, it means that the delay on the loop has decreased, and at the same time, the delay on the loop has decreased by one frame. Since the value may fluctuate around an integral multiple, the initial value controllers 37 and 39 are controlled. Divider 47
divides the output value of the delay counter 41 by the output value of the comparison value storage section 43 and sets the quotient in the comparison value storage section 43 if the output value of the delay counter 41 is larger.

In the initial state, the memory 21 is driven with a capacity for one frame. That is, when the count value of the reception counter 11 and the transmission counter 15 reaches "400", the next count value is initialized to "1".

The count value of the transmission counter 15 is sent to the memory control unit 19, and the memory control unit 19 gives a reading address to the memory 21a, and the corresponding data is read out from the memory 21a, and is sent to the transmission line 5 via the transmission shift register 17. Transmission data is sent.

In this case, the last bit X of the data field of the frame is “0#”.
When the frame header is detected by the H detection unit 9, the count value issued by the reception counter 11 becomes the write address of the memory 21a, and the reception data inputted via the reception shift register 7 according to this address is written to the memory 21a.
written to a.

The delay counter 41 measures the time from transmitting a frame to receiving the frame. The comparator 45 compares the output value of the delay counter 41 and the comparison value storage section 43, and if the output value of the delay counter 41 is smaller than the set comparison value of the comparison value storage section 43, that state is maintained.

Further, when the output value of the delay counter 41 is larger than the output value of the comparison value storage section 43 by the divider 47, the quotient is reset in the comparison value storage section 43.

Thereafter, the comparator 45 compares the delay value from when the X-0 frame is transmitted to when it is received with the set comparison value. As a result of this comparison, if the delay value indicated by the delay counter 41 is larger than the comparison value set in the comparison value storage section 43, the memory 21a
is driven with a capacity for one frame.

When the delay value indicated by the delay counter 41 becomes smaller than the output value of the comparison value storage unit 43, it means that the delay on the transmission path has decreased, and at the same time, the delay on the transmission path can fluctuate around an integer multiple of one frame. There is sex. Therefore, the memory 21a is driven with a capacity for two frames. That is, depending on the output of the comparator 45, the initial value control unit 37 alternately uses "1" and "401" as the initial value of the reception counter 11. The initial value control unit 39 also controls the transmission counter 15.
The control that had been returning to the initial value 1 when the count number is 400 is shifted to the control that is returning to the initial value l when the count number is 800. Therefore, the memory controller 19 gives addresses 1 to 800 to the memory 21a, and the memory 21a is driven with a capacity for two frames.

FIG. 4 is a diagram showing the amount of data held in the memory 21a when three frames circulate on the transmission path.

In the figure, FHo%FH1 and PH2 indicate three types of frame headers. When the output value of the delay counter 41 is larger than the output value of the comparison value storage section 43, the data for three frames minus the data circulating on the loop is less than one frame, so the memory 21a stores the data for one frame. It is sufficient to drive with capacity (Figure 4 (a)
).

When the output value of the delay counter 41 becomes smaller than the output value of the comparison value storage section 43, the loop one round time (delay on the transmission path)
There is a possibility that the number of frames changes around an integer multiple of one frame, and in the past, frames were sometimes lost. However, in this embodiment, in such a case, the memory 21a is switched to a capacity for two frames, so as shown in FIG. Even if there is more than one frame, it is stored in the memory 21a.
data can be retained to prevent data loss.

Note that the present invention can be modified in various ways within the scope of its technical idea.

For example, in this embodiment, the slot has a data field of 8 bits and a control field of 2 bits, but it may also have an 8-bit data field and a 1-bit control field.

Further, the number of slots in one frame may be, for example, 1538 slots. In this case, the reception counter 11 and transmission counter 15 are advanced every 9 bits, and the comparison value is 1536,
The value obtained by dividing the delay value by 1536 may be set in the comparison value storage section 43 as a comparison value.

Furthermore, the memory 21a does not necessarily need to be used continuously. For example, if one frame has 1536 slots, the initial value of the reception counter due to reception in the frame header is set alternately between 0 and 2048, and the transmission counter is also set from 0 to 15.
When it reaches 35, initialize the next one to 2048, and then 35
After proceeding to step 83, it may be initialized to 0.

Further, reading and writing to the memory 21a does not necessarily have to be performed in units of slots, and may be performed in units of 4 slots, for example. At this time, the reception counter 11 and transmission counter 15 may be controlled so that the address advances every four slots.

Also, the time for one round of the loop does not need to be 125 μs,
For example, it may be 10 μs or 100 μs.

[Effects of the Invention] As described in detail above, according to the present invention, even when the loop time is close to an integral multiple of the frame period, highly reliable communication can be performed without the risk of data loss.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a control station of a loop communication system according to an embodiment of the present invention, and FIG.
Figure 3 is a frame format diagram, Figure 4 is a diagram showing transmission and reception timing, Figure 5 is a schematic configuration diagram of a loop communication system, and Figure 6 is a diagram showing the configuration of a conventional control station. FIG. 7 is a diagram showing a frame format in the conventional example, and FIGS. 8 and 9 are diagrams showing transmission and reception timing in the conventional example. 11...Reception counter 15...Transmission counter 19...Memory control unit 21a...Memory 37.39...・Initial value control unit 41...Delay counter 43...Comparison value storage unit 45...Comparator 47... ...Divider applicant Toshiba Corporation Patent attorney Sasa Suyama - Figure 3

Claims (1)

[Claims] (1) A control station and a plurality of stations are connected in a loop via a transmission path, and communication is performed between each station by circulating frames on the transmission path, and the number of frames circulating on the transmission path is In a variable loop communication system, the control station includes a memory having a capacity for two frames, a detection means for detecting a decrease in the number of frames circulating on a transmission path, and a memory that normally has a capacity for one frame. and memory control means for driving the memory at a capacity of two frames when the detecting means detects a decrease in the number of frames on the transmission path.