JPH01209151A - pattern generation circuit - Google Patents

Abstract

PURPOSE:To enhance the reading and conversion speeds of pattern data, by providing a pattern data converting circuit within a pattern generating circuit to directly transmit the converted pattern data to a memory such as an RAM. CONSTITUTION:The code data of a character wished to read is outputted to a bus 11 and conversion data indicating pattern conversion is outputted to a bus 13 to be written in a character pattern generator 5 on the basis of a control signal 10. A pattern data memory part 2 outputs the corresponding pattern data 12 to a pattern converting part 3. A selector 31 controls the reading of a register (32 X 32 bits) 30 on the basis of the conversion data given from the bus 13 and performs pattern conversion to output the converted data to a bus 14. A CPU 1 outputs an address signal to an RAM 4 by an address bus 15 and outputs a writing signal to the RAM 4 on the basis of a control signal 17. The converted pattern data is written in the desired address of the RAM 4. Conversion data indicating the next conversion is outputted to the bus 13 and these operations are repeated 32 times and the converted pattern data corresponding to one character is read and can be stored in the RAM 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pattern generation circuit that inputs code information such as a character code and outputs pattern data thereof.

[Prior Art] In a conventional pattern generation circuit, a character code, etc. sent from a CPU is input, and pattern data is output in accordance with a read request. For example, when this output pattern data is read as horizontal raster scan data of a character pattern, the character pattern is 24×24
Assuming that the CPU is configured with an 8-bit data bus, data for one line is read out in three read processes, and pattern data for one character is read out in 72 (3×24) read processes. .

[Problem to be solved by the invention] In this way, when the CPU reads out one character pattern,
If it is necessary to perform multiple read processes and further perform pattern conversion processes such as rotation or enlargement on these pattern data, store the pattern data in a memory such as RAM, and then read the pattern data again. Therefore, there is a problem in that a lot of time is required for pattern reading, pattern conversion, etc., resulting in a decrease in the processing time of the entire apparatus.

The present invention has been made in view of the above conventional example, and reads and converts pattern data by providing a pattern data conversion circuit in the pattern generation circuit and directly transferring the converted pattern data to a memory such as a RAM. An object of the present invention is to provide a pattern generation circuit with improved speed.

[Means for Solving the Problems] In order to achieve the above object, the pattern generation circuit of the present invention has the following configuration. That is, the pattern generation circuit inputs code information and conversion information of the code information and outputs corresponding pattern information, and includes a storage means for storing pattern information such as characters in correspondence with the code information, and the storage means. and converting means for converting the pattern information outputted from the converter according to the conversion information.

Further, a pattern generation circuit according to another invention has the following configuration. That is, a pattern generation circuit inputs code information and conversion information of the code information and outputs corresponding pattern information, comprising a storage means for storing pattern information such as characters in correspondence with the code information, and the storage means. The apparatus includes a converting means for converting pattern information outputted from the converter according to the conversion information, and a transfer means for inputting an address of a memory storing the pattern information and transferring the converted pattern information to the address of the memory.

[Operation] In the above configuration, the pattern information output based on the input code information is converted and outputted according to the input conversion information from the storage means that stores pattern information such as characters corresponding to the code information. It works like this.

According to another configuration, pattern information output from a storage means that stores pattern information such as characters in correspondence with code information is converted in accordance with conversion information. Along with that,
It operates by inputting the address of a memory that stores pattern information and transferring the converted pattern information to that memory address.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[Description of Memory Circuit (FIGS. 1 to 5)] FIG. 1 is a diagram showing the configuration of a memory circuit according to an embodiment and connections with a CPU, RAM, etc.

In the figure, 1 is a CPU that outputs code information to the character storage section 2 to instruct reading of pattern data from the pattern data storage section 2, and outputs desired data conversion instructions to the pattern converter 3, such as a microprocessor. ROM 1 shown in the flowchart of FIG.
It operates according to the control program stored in -1. 5
1 is a character pattern generator of the embodiment, which inputs code information from cput through bus 11 and control information through bus 13, performs conversion instructed by the control information, and outputs pattern data to bus 14. Reference numeral 2 denotes a pattern data storage unit such as a ROM or disk, which stores a plurality of pattern data corresponding to character codes, and inputs code information and a control signal 10 instructing reading from the CPU to read the corresponding pattern data. 12 is output to the pattern converter 3.

3 is a pattern converter which converts the pattern data 12 sent from the pattern data storage unit 2 based on conversion instruction information instructed by the CPU 1 via the bus 13;
The converted pattern data 14 is transferred to the RAM via the bus 14.
4 or output to CPUI. Here, it is assumed that the pattern converter 3 has a 32.times.32 bit register and is capable of inverting pattern information and rotating pattern data by 90 degrees, 180 degrees, 270 degrees, etc. 15 is CPUI
16 is its data bus, and 17 is a control signal from the CPU 1 instructing writing to or reading from the RAM 4.

With the above configuration, cput outputs to the character pattern converter 5 a control signal 10 consisting of code information such as a character to be read, conversion information of its pattern data, and a signal for instructing writing or reading. As a result, the character pattern generator 5 inputs the code information from the bus 11 in synchronization with the write signal (R/W) of the control signal 10, and inputs the conversion information from the bus 11.
3, the corresponding pattern data is converted and output to the bus 14.

FIG. 2 is a diagram showing the human output signals of the character pattern memory.

Reference numeral 20 denotes a character pattern memory (ROM) as an example of the pattern data storage section 2, into which a control signal 10 and code information from a bus 11 are input, and corresponding character pattern data 12 is output. The control signal 10 includes AS (address strobe signal), CLK (clock signal), and R/
Contains W (read/write signal), etc., and R/W
The code information is captured in synchronization with the falling edge of the signal, and the 32x32 dot pattern data corresponding to the code information is captured in one piece.
Outputs 2.

FIG. 3 is a diagram showing the configuration and input/output signals of the pattern converter 3 of the first embodiment.

30 is a bit manipulation unit (BM
A 32×32 bit register constituting U) stores one character pattern, and the selector 31 changes the reading direction, etc., and outputs it as a converted pattern. The selector 31 inputs the control signal 10 and control information instructing conversion from the bus 13, rotates the pattern data 12, etc., and outputs the rotated pattern data 12 to the bus 14.

For example, in the case of FIG. 3, when the selector 31 is set to a mode in which the data in the register 30 is converted to Y-axis symmetrical data (horizontal inversion) and output, the selector 31
inputs data 32 of 1024 bits (32×32 bits), switches the output order, and outputs the data in the order from DXo to DX31 to DX31 to DXO. The Y-axis symmetrical inversion result thus output and stored in the RAM 4 is shown in FIG. Note that the address stored in the RAM 4 at this time is given from the CPU via the address bus 15.

FIG. 5 is a flowchart showing the pattern reading process of the CPU in the first embodiment.
is stored in.

The code information of the character you want to read in step S1 is sent to the bus 11.
In step S2, conversion information instructing how to convert the pattern is outputted to the bus 13 and written to the character pattern generator 5 using the control signal 10. As a result, the pattern data generator 2 generates the corresponding pattern data 12.
is output to the pattern converter 3. Further, in the pattern converter 3, a selector 31 controls reading of the register 30 based on the conversion information given from the bus 13, performs pattern conversion, and outputs the result to the bus 14.

Therefore, in step S3, the CPUI outputs an address signal to the RAM 4 via the address bus 15, and in step S4, outputs a write signal to the RAM 4 via the control signal 17. As a result, the converted pattern data, for example, 32 bits, is written to a desired address in the RAM 4. Then, in step S5, it is checked whether the output of the pattern data has been completed, and if it has not been completed, the process returns to step S2, and conversion information instructing the next conversion is output to the bus 13, and the above-described operation is performed. By repeating these operations 32 times, one character's worth of converted pattern data can be read out and stored in the RAM 4.

FIG. 6 is a diagram showing the configuration of a pattern converter according to the second embodiment. Parts common to those in FIG. 3 are indicated by the same symbols, and their explanation will be omitted.

34 is a memory controller which inputs the conversion information from the CPUI and the start address to be written in the RAM 4 from the bus 13 in synchronization with the control information 10. outputs the selection signal 33 to the selector 31 according to the conversion information, and
Address 14' to be stored in 4 and write signal 18 are output.

The operation of the CPU at this time will be explained using the flowchart shown in FIG.

Enter the character code of the character you want to read in step SIO on bus 1.
1, and the conversion information is output to the bus 13 in step Sit. Then, a write signal (R/W signal) is set to low level and outputted as the control signal 10. As a result, the character code is stored in the pattern data storage section 2, and the conversion information is stored in the memory controller 34. Next, in step S12, the start address to be written to the RAM 4 is output to the bus 13, and the control signal 10 is output to the memory controller 34.
Set to .

FIG. 8 is a flowchart showing the control operation of the memory controller 34.

The process waits for conversion information to be input in step S20, and when the conversion information is input, the process proceeds to step S21, where conversion information for the bus 13 is input and stored. Next, in step S22, it is checked whether an address signal has been input, and if so, in step S23, the address signal on the bus 13 is input and stored.

In step S23, the selection signal 33 is output based on the conversion information, and in step S25, the address 14' of the RAM 4 and the write signal 18 are output to the RAM 4, and the converted pattern data 14 is written in the RAM 4. Thus step 32
At step 6, it is checked whether all data has been output, and steps 324 to 326 are repeatedly executed while updating the address of the RAM 4 until the data output is completed.

As described above, according to this embodiment, by providing a converter for converting pattern data in the character pattern generator, it is possible to directly read converted pattern data.

In addition, by equipping the character pattern converter with a circuit that addresses the memory and sequentially writes it, the CPU can store all converted pattern data in the memory by simply outputting the character code information, conversion information, memory storage address, etc. be able to.

Although this embodiment has been described in the case of 32×32 bit dot pattern data, vector information called an outline font, for example, can be handled in the same way. In this case, the BMU also becomes a multiplication circuit with vector information, rather than a dot conversion circuit. This processing circuit is particularly effective in the case of outline fonts, since the processing speed is particularly low.

[Effects of the Invention] As described above, according to the present invention, since converted pattern data can be read out, pattern data reading and conversion processing are facilitated.

According to another invention, it is possible to perform the conversion specified by the pattern information and write it directly to the memory, so that the CPU
This has the advantage that the read processing can be easily executed.

[Brief explanation of the drawing]

Figure 1 shows the configuration of the memory circuit of the embodiment, as well as the CPU and RAM.
Figure 2 shows the input/output signals of the character pattern memory, Figure 3 shows the configuration of the pattern converter and input/output signals, and Figure 4 shows the input/output signals of the RAM. Figure 5 shows the CPU
6 is a block diagram showing the schematic configuration of the pattern converter of the second embodiment. FIG. 7 is a flowchart showing the processing of the CPU of the second embodiment. FIG. 8 is a flow chart of the memory controller. 3 is a flowchart showing processing. In the figure, 1...CPU, 2...Character information storage unit, 3...
...Pattern converter, 4...RAM, 10...Control signal, 11.13, 14.14'...Bus, 1゛2.
...Pattern data, 15...Address bus, 20.
...Character pattern memory, 30...Register, 31.
... Selector, 34... Memory controller. Figure 4 Spring 3 t pin kuo - 關

Claims (2)

[Claims] (1) A pattern generation circuit that inputs code information and conversion information of the code information and outputs corresponding pattern information, comprising a storage means for storing pattern information such as characters in correspondence with the code information, and the memory. A pattern generation circuit comprising: conversion means for converting pattern information outputted from the means according to the conversion information. (2) A pattern generation circuit that inputs code information and conversion information of the code information and outputs corresponding pattern information, comprising a storage means for storing pattern information such as characters in correspondence with the code information, and the memory. A conversion means for converting the pattern information outputted from the means according to the conversion information, and a transfer means for inputting an address of a memory storing the pattern information and transferring the converted pattern information to the address of the memory. A pattern generation circuit featuring: