JPH01210996A - Address control circuit for display device - Google Patents

Abstract

PURPOSE:To facilitate the microprogram control synchronized with the display control and to simplify description of a microprogram by giving a prescribed bit constitution to the address input of a microprogram memory. CONSTITUTION:A microprogram memory 1 is connected to a clock generating circuit 4 and a synchronizing signal generating circuit 3, and the address input of the memory 1 consists of low order two bits A0 and A1 of the output from the circuit 4, two following bits A2 and A3 of horizontal and vertical synchronizing signal outputs from the circuit 3, and high order bits A4 and A5, etc. Consequently, the microprogram control synchronized with the display control is easily and surely performed and description of a microprogram is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address control circuit for easily performing microprogram control B in synchronization with screen display in display devices such as graphic displays and character displays.

[Summary of the Invention J The present invention is an address control circuit for easily performing microprogram control synchronized with screen display in display devices such as graphic displays and character displays, and includes a microprogram memory and a control circuit. It consists of a synchronization signal generation circuit and a clock generation circuit, and the clock from the clock generation circuit is input to the lower two bits of the address input of the microprogram memory, and the horizontal synchronization signal and vertical synchronization signal are input to the next two bits. By inputting a signal and inputting the execution address of the next cycle from the control circuit into the higher-order bits, the microprogram area is divided into state blocks of clock and synchronization signals.

This facilitates microprogram control in synchronization with screen display and facilitates microprogram writing. Furthermore, synchronous control of several types of peripheral logic and control of several types of operations within the same logic can be easily controlled by a microprogram.

[Conventional technology]

Conventionally, synchronization control with screens such as graphic displays and character displays has been performed by determining vertical synchronization signals and horizontal synchronization signals as state inputs, and after performing state control judgments with other state inputs, microprograms are executed using counters, etc. Count the number of instructions given to memory etc.
A method of controlling read timing was commonly used.

[Invention or problem to be solved]

Conventional microprogram address control synchronized with the display screen is configured using counters and many other control logics as described above, so it requires a large amount of hardware (
There was a problem that the control sequence was complicated.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a microprogram address control circuit for solving the above-mentioned problems and easily performing microprogram control synchronized with the screen in display devices such as graphic displays and character displays.

[Means to solve the problem]

In order to solve the conventional problems, the present invention consists of a microprogram memory, a control circuit, a synchronization signal generation circuit, and a clock generation circuit, and the lower two bits of the address input of the microprogram memory are By inputting the clock from the clock generation circuit, inputting the horizontal synchronization signal and vertical synchronization signal into the next two bits, and inputting the execution address of the next cycle from the control circuit into the upper pins. , the microprogram area is divided and controlled into clock and synchronization signal status blocks.

[Effect]

A series of control commands are written into the microprogram memory from the CPU bus during the initial operation of the device according to a write control signal output from the write control circuit.

Further, the system clock and the frequency-divided clock of the device constituted by the clock generation circuit are inputted to the lower address of the microprogram memory. Further, the horizontal synchronization signal and vertical synchronization signal output from the synchronization signal generation circuit are input to the next address input 2 bits of the microprogram memory, and the next address of the microprogram memory output from the control circuit is the microprogram memory. The remaining bits of memory are filled in. A control command read from the microprogram memory according to the address input is input to a control circuit, and the control circuit outputs the control command to each peripheral logic.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

In FIG. 1, a microprogram memory 1 is a memory that stores microprograms for controlling peripheral logic in synchronization with screen display cycles, such as a graphic display and a character display. The write control circuit 5 connects the CPU through the CPU bus 2.
At the same time, the address inputted from 7 is decoded into a write address, and at the same time, a microprogramming program write control signal is generated from the write control signal inputted through the CPU bus a and the write address, and both signals are outputted to the control line j. The CPU bus a also supplies addresses, data, control signals, etc. output from the CPU 7 to peripheral logics not directly related to the present invention.

The microprogram memory 1 outputs the CPU 7 according to the microprogram write signal and the write address input from the controller 411vAj.
Writes the microprogram input from U bus a. The above operations are executed when the circuit is initialized.

The clock generation circuit 4 generates a basic operation clock φ as shown in FIG. 4, and divides this basic operation clock φ to generate a basic operation clock 1 shown in FIG.
They are output as signals lb and c, respectively.

The synchronization signal generation circuit 3 generates a vertical synchronization signal (shown in FIGS. 2 and 4) at the display control timing of the display device 6 based on the basic operation clock 1 input from the signal line C.
Vsync) and horizontal synchronization signal (Hsync),
The former is output to the signal line e, and the latter is output to the signal vAd. In FIG. 4, the timing in the upper row is the display control timing) (the relationship between sync and Vsync.
The four timings in the middle are display control timing Hs.
ync, Vsync, and the timings of the aforementioned basic operation clock 1 and basic operation clock φ.

The four types of signals are completely synchronized. Further, the timings in the lower row are an enlarged view of the basic operation clock 1 and the basic operation clock φ shown in the middle row, and an example of the synchronous operation when operating the peripheral logic according to the present invention.

An example will be explained in the second half of this embodiment.

The control circuit 2 adjusts the phase of the address (netast address) indicating the command of the next cycle inputted through the control line mvAr by using the basic operation clock 1 and the basic operation clock φ inputted through the control line. After being delayed by a cycle, it is output to address bus h. That is, in the phase relationship shown in the lower part of FIG. 4, the control command stored at the address on the microprogram memory 1 indicated by the netast address read out at the first φ is output at the second φ1. The phase is controlled so that the

The microprogram memory 1 inputs the basic operation clock of the control amb as an address A, and further inputs the basic operation clock of the control amb as an address A.
The horizontal synchronization signal of address A.

The vertical synchronizing signal on the control line e is input as address A. Furthermore, the execution address of the next cycle input from the address bus h is set to addresses A4 to A.
, enter as . n is microprogram memory 1
This is a variable determined by the memory size of .

Through the address control described above, the microprogram memory 1 reads out the control commands stored internally according to the addresses inputted as Aφ to A, and the execution address of the next cycle (netast address), and outputs the control line f. Output to. Netast addresses are treated the same as above,
This process is repeated for each cycle. The contents of the microprogram are comprised of control instructions for the peripheral circuit 5 and netast addresses, as shown in FIG. Each bit of address Aφ to A11 of microprogram memory 1 is as follows: memory address Aφ is basic operating clock φ, A1 is basic operating clock 1, A2 is Hsync, and A is V.
sync, A4 to A, and l correspond to the next address read in the previous cycle and phase-controlled by the control circuit 2. Due to this correspondence, each next address is divided into four blocks depending on the states of Hsync and Vsync, and each block is further divided into four blocks according to the basic operation clock 1 and the basic operation clock φ.

The control circuit 2 inputs the control code on the control line f and the status display signal i output from the peripheral circuit 5 of the display device to the control line i, and transmits the control code to the peripheral circuit 5 according to the status of l. 6 peripheral circuit 6 outputs as control vAg.
It operates according to the control command input as IJ'b'Ag. The control line g indicates the type and number of controls of the peripheral circuit 6, and
The number varies depending on the control method. Accordingly, the control line f
The number of lines and the bit width of the control instructions shown in FIG. 3 change.

Although each component shown in the present invention operates as described above, address control in the microprogram memory 1 will be explained below. FIG. 2 is an explanatory diagram of the vertical synchronization signal and the horizontal synchronization signal. Since each signal is defined by the prior art, detailed explanation in this section will be omitted. - For boat fishing, in display devices such as graphic displays, Vsync, Vmr (vertical side back porch), ■□(
Vertical side front porch) + Hsync, HIF (horizontal side front porch), VFP (Various calculation processing is performed during each non-display period of horizontal side front porch, and the processing during display is Hsync, Vsync according to the timing of this example. In FIG. 2, this is performed when both are "H".As described above, the microprogram memory 1 performs At for each next address.

It is divided into four blocks by Hsync and Vsync input to A, and each of them is further divided into four blocks by the basic clock 1 and basic operation clock φ input to Aφ and AI.

This makes it easy to write and process processes such as jumping from the current state to another address depending on the Vsync and Hsync states, or jumping to the same address as the current address (loop). Processing for each state of Hsync and description of the processing can be easily performed. Furthermore, by writing the states of Vsync and Hsync at each address as shown in the example in Figure 4,
In this example, four types of circuits can be independently controlled in units of cycles of the basic operation clock 1.

In the address control of the lower two bits, it is possible to increase the number of states by increasing the number of focuses depending on the period of the basic operation clock 1, the processing speed of the peripheral device group, the processing speed of the microprogram memory 1, etc.

〔Effect of the invention〕

As described above, the present invention facilitates microprogram control in synchronization with display control in display devices such as graphic displays and character displays, and further simplifies the writing of microprograms. Furthermore, by dividing the basic clock within the same device, it is possible to operate several peripheral logics (peripheral devices) completely independently using different program descriptions, or to make the same device perform several different types of operations. Become.

Furthermore, as described above, in synchronized control of graphic display devices and character display devices, display periods and non-display periods are often divided and controlled differently, but the present invention can easily achieve this. It becomes realizable.

The present invention has the effects described above.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the relationship between the screen of a display device and a synchronization signal, and FIG. 3 is a diagram showing a microprogram storage state in the present invention shown in the embodiment.
FIG. 4 is a timing diagram of a synchronization signal and a basic clock shown in the embodiment. 1... Micro program memory 2... Control circuit 3... Synchronous signal generator 4... Clock generator 5... Write control circuit and above Applicant: Seiko Electronics Industries, Ltd.

Claims (1)

[Claims] In a display device such as a graphic display or a character display, a microprogram memory that stores a synchronization signal generation circuit for controlling screen display and a microprogram for controlling the operation of internal logic of the device. a means for transmitting the control command read from the microprogram memory to the internal logic according to a state input from the internal logic; a control circuit having means for transmitting data to the program memory; and a clock generation circuit that generates a clock for synchronously controlling internal circuits, and a clock from the clock generation circuit is input to the lower bits of the address input of the microprogram memory. is input, a horizontal synchronization signal and a vertical synchronization signal are input to the next two bits, and the execution address of the next cycle transmitted from the control circuit is input to the bits higher than the aforementioned four bits to execute the microprogram. An address control circuit for a display device, characterized in that it controls reading from a memory.