JPH01213896A - Uv-prom erasing device - Google Patents

Uv-prom erasing device

Info

Publication number
JPH01213896A
JPH01213896A JP63039842A JP3984288A JPH01213896A JP H01213896 A JPH01213896 A JP H01213896A JP 63039842 A JP63039842 A JP 63039842A JP 3984288 A JP3984288 A JP 3984288A JP H01213896 A JPH01213896 A JP H01213896A
Authority
JP
Japan
Prior art keywords
sample
erased
erasing
data
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63039842A
Other languages
Japanese (ja)
Inventor
Shinichiro Akeyama
明山 慎一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63039842A priority Critical patent/JPH01213896A/en
Publication of JPH01213896A publication Critical patent/JPH01213896A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To easily execute the confirmation of a sample, for which erasing is completed, and accordingly to erase a waste to irradiate ultraviolet rays to the erased sample for an excess time by additionally providing a detecting means to detect erase end in a UV-PROM erasing device which can be erased by the ultraviolet rays. CONSTITUTION:The erasing device is composed of a CPU1, a ROM2, to which a series of processing programs are written, a RAM3 for work, a ultraviolet rays irradiating device 4, an IC setting stand 5, a turning-off completing lamp turning-on device 6, an address/data bus 7 and a latch circuit 8. Thus, a sample A of the setting stand 5 is selected and a first address is given from the CPU1. Then, an output is accumulated in a latch A of the circuit 8 and contents are read. Whether the contents are data to be erased by the CPU1 or not is compared. In case of the erased data, the next address is given to the sample A. Such operation is repeated to all the addresses and when the data are erased, the CPU1 is operated and a lamp A is turned on. Thus, the erasing is executed in a short time.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はUV−PROM (Ultra Violet
 −ProgranableRead 0nly Ma
nory)の消去装置に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to UV-PROM (Ultra Violet
-ProgranableRead 0nly Ma
(nory) erasing device.

〔従来の技術〕[Conventional technology]

従来のUV−PROMの消去装置は、紫外線ランプの下
にUV−PROMのICを置き、適当な時間このICに
紫外線を照射することにより、UV−P ROM内のデ
ータを消去していた。
A conventional UV-PROM erasing device erases data in the UV-PROM by placing the UV-PROM IC under an ultraviolet lamp and irradiating the IC with ultraviolet light for an appropriate period of time.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

前述した従来のUV−PROM消去装置は、消去終了時
刻を予測できないため、消去確認のためKEPROMラ
イタにて確認しなければならず、万一完全に消去されて
いない場合に、再度確認して、消去しなければならなく
なるため、非常に面倒であった。また、完全に消去され
ていた場合においても、消去が終わってから消去確認ま
での時間が無駄であるという欠点があった。
The above-mentioned conventional UV-PROM erasing device cannot predict the end time of erasure, so it must be confirmed with a KEPROM writer to confirm erasure.If it is not completely erased, check again. It was very troublesome because it had to be deleted. Furthermore, even if the data has been completely erased, there is a drawback that the time from the completion of erasure to confirmation of erasure is wasted.

本発明の目的は、前記欠点が解決され、極めて容易に完
全消去できるようにしたUV−PROM消去装置を提供
することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a UV-PROM erasing device which solves the above-mentioned drawbacks and allows complete erasing with extreme ease.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のUV−PROM消去装置の構成は、消去終了を
検知する手段を設けたことを特徴とする。
The configuration of the UV-PROM erasing device of the present invention is characterized in that means for detecting the completion of erasure is provided.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例のUV−PROM消去装置の
ブロック図である。同図において、本装置は、CPUI
と、一連の処理プログラムの書かれたROM2と、ワー
ク用RAM3と、紫外線照射装置4と、ICを置くため
のサンプル台5と、消去完了ランプ点灯装置6と、アド
レス/データバス7とを含み、構成される。
FIG. 1 is a block diagram of a UV-PROM eraser according to an embodiment of the present invention. In the same figure, this device has a CPU
, a ROM 2 in which a series of processing programs are written, a work RAM 3, an ultraviolet irradiation device 4, a sample stand 5 for placing an IC, an erase completion lamp lighting device 6, and an address/data bus 7. , configured.

本実施例では、試料数を2とし、それぞれサンプルA、
Bとする。
In this example, the number of samples is 2, and samples A and A, respectively.
Let it be B.

まず、サンプル台5のサンプルAが選択され、最初のア
ドレスがCPUIによって与えられ、サンプルAのデー
タがデータラッチ回路のラッチAに蓄えられる。次に、
ラッチAの内容が読み出され、CPU1により消去され
たデータか否か即ちデータFFHであるか否か比較され
る。その結果、消去されたデータである場合は、サンプ
ルAに対して次のアドレスが与えられ、前述のごとく比
較され、全アドレスに対して全て消去されたデータであ
れば、CPU1はランプ人を点灯させる。
First, sample A on the sample stage 5 is selected, a first address is given by the CPU, and the data of sample A is stored in latch A of the data latch circuit. next,
The contents of latch A are read out and compared to determine whether the data is erased by the CPU 1, that is, data FFH. As a result, if the data is erased, the next address is given to sample A and compared as described above, and if the data is erased for all addresses, CPU 1 turns on the lamp. let

前記の比較中に消去されていないデータがあった場合は
、サンプルAのチエツクを終え、次のサンプルBにおい
て前述と同様の処理を行う。この処理を全サンプルが消
去完了となるまで繰り返す。
If there is any data that has not been erased during the comparison, the check for sample A is finished, and the same process as described above is performed for the next sample B. This process is repeated until all samples are completely erased.

第2図は前述の装置の処理フロー図である。同図におい
て、 本装置の処理は、開始11から一連の動作が始まシ、終
了28にて、消去が終了する。
FIG. 2 is a processing flow diagram of the above-mentioned apparatus. In the figure, in the process of this apparatus, a series of operations starts from start 11, and erasing ends at end 28.

まず、アドレス初期化処理12を行い、サンプル台15
のサンプルAのデータを読出す処理13を行い、消去さ
れたデータか否か即ちFFHであるか否かの判断処理1
4が行われ、(YES)の場合は次の最終アドレスか否
かの判断処理15に送られ、〔NO3の場合は、サンプ
ル台のサンプルBは消去完了か否かの判断処理18を介
して、〔YES)の場合は、アドレス初期化処理12へ
送られ、[NOIの場合は、次のアドレス初期化処理1
9へ送られる。
First, address initialization processing 12 is performed, and the sample stand 15
A process 13 of reading out the data of sample A is performed, and a process 1 of determining whether the data is erased or not, that is, whether it is FFH or not.
4 is performed, and if (YES), the data is sent to the next final address judgment process 15; [If NO3, the sample B on the sample stand is sent to the judgment process 18 to see if the erasure is completed or not. , [If YES], it is sent to the address initialization process 12; [If it is NOI, it is sent to the next address initialization process 1.
Sent to 9.

最終アドレス[:YES)の場合は、サンプルAの消去
完了ランプAを点灯させる処理16を行い、〔NO3の
場合は、アドレスインクリメント処理17を介して、処
理13にもどされる。処理16を通した後、サンプルB
は消去完了か否かの判断処理を通し、(YES)の場合
、終了28となシ、〔NO3の場合は、サンプルBにつ
いて、処理12乃至処理18と同様な処理19乃至処理
27が行われる。サンプルAは消去完了か否かの判断処
理24が(NOIの場合は、アドレス初期化処理12に
もどされる。[:YES]の場合、終了28となる。
If the final address is [:YES], processing 16 is performed to turn on the erase completion lamp A of sample A, and if [NO3], the process returns to processing 13 via address increment processing 17. After passing through treatment 16, sample B
If the result is NO3, the same processes 19 to 27 as the processes 12 to 18 are performed for sample B. . If the determination process 24 of whether or not the sample A has been erased is NOI, the process returns to the address initialization process 12. If [:YES], the process ends 28.

第1図の実施例に、さらにタイマーを内蔵することによ
シ、サンプルの消去時間を測定できるため、消去時間の
評価に一層便利である。
By incorporating a timer in the embodiment shown in FIG. 1, it is possible to measure the erasing time of the sample, making it even more convenient to evaluate the erasing time.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、消去完了となったサン
プルが一目で分かり、また消去後PROMライタでの消
去確認をする必要がないため、時間の節約ができる効果
があり、さらに消去完了となったサンプルに余分な時間
紫外線照射することがなくなるため、最短時間で消去で
きる効果があシ、特にタイマーを内蔵した場合は人手を
介さすに消去時間の蛛;11定ができる効果がある。
As explained above, the present invention has the effect of saving time because it is possible to see at a glance which samples have been erased, and there is no need to confirm the erasure with a PROM writer after erasing. Since there is no need to irradiate the sample with ultraviolet rays for an extra period of time, it has the effect of erasing the sample in the shortest possible time.In particular, when a timer is built in, the erasing time can be kept constant without manual intervention.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例のUV−PROM消去装置を
示すブロック図、第2図は第1図のUV−PROM消去
装置の処理フロー図である。 1・・・・・・CPU、2・・・・・・I’tOM、3
・・・・・・RA M 。 4・・・・・・紫外線照射装置、5・・・・・・サンプ
ル台、6・・・・・・消去完了ランプ点灯装置、7・・
・・・・アドレス/データバス、8・・・・・・データ
ラッチ回路、11・・・・・・開始、12,19・・・
・・・アドレス初期化処理、13−・・・・・サンプル
Aのデータを読み出す処理、14,21・・・・・・F
FHか否かの判断処理、15.22・・・・・・最終ア
ドレスか否かの判断処理、16.23・・・・・・完了
ランプを点灯させる処理、17.25・・・・・・アド
レスインクリメント処理、18.27・・・・・・消去
完了か否かの判断処理、28・・・・・・終了。 代理人 弁理士  内 原   音 第1回 ?JZIl
FIG. 1 is a block diagram showing a UV-PROM erasing device according to an embodiment of the present invention, and FIG. 2 is a processing flow diagram of the UV-PROM erasing device of FIG. 1...CPU, 2...I'tOM, 3
...R.A.M. 4... Ultraviolet irradiation device, 5... Sample stand, 6... Erase completion lamp lighting device, 7...
...Address/data bus, 8...Data latch circuit, 11...Start, 12, 19...
...Address initialization processing, 13-...Processing to read data of sample A, 14, 21...F
Processing to determine whether it is FH or not, 15.22...Processing to determine whether it is the final address, 16.23...Processing to turn on the completion lamp, 17.25... - Address increment processing, 18. 27... Judgment processing whether erasure is complete, 28... End. Agent Patent Attorney Uchihara Oto 1st session? JZIl

Claims (1)

【特許請求の範囲】[Claims] 紫外線にて消去可能なUV−PROM消去装置において
、消去終了を検知する手段を設けたことを特徴とするU
V−PROM消去装置。
A UV-PROM erasing device capable of erasing with ultraviolet rays, characterized in that it is provided with means for detecting completion of erasing.
V-PROM eraser.
JP63039842A 1988-02-22 1988-02-22 Uv-prom erasing device Pending JPH01213896A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63039842A JPH01213896A (en) 1988-02-22 1988-02-22 Uv-prom erasing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63039842A JPH01213896A (en) 1988-02-22 1988-02-22 Uv-prom erasing device

Publications (1)

Publication Number Publication Date
JPH01213896A true JPH01213896A (en) 1989-08-28

Family

ID=12564220

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63039842A Pending JPH01213896A (en) 1988-02-22 1988-02-22 Uv-prom erasing device

Country Status (1)

Country Link
JP (1) JPH01213896A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02123800U (en) * 1989-03-15 1990-10-11

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02123800U (en) * 1989-03-15 1990-10-11

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