JPH01214111A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01214111A JPH01214111A JP63040100A JP4010088A JPH01214111A JP H01214111 A JPH01214111 A JP H01214111A JP 63040100 A JP63040100 A JP 63040100A JP 4010088 A JP4010088 A JP 4010088A JP H01214111 A JPH01214111 A JP H01214111A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- silicon thin
- island
- crystal
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000010409 thin film Substances 0.000 claims description 63
- 239000013078 crystal Substances 0.000 claims description 52
- 238000000034 method Methods 0.000 claims description 45
- 229910052710 silicon Inorganic materials 0.000 claims description 40
- 239000010703 silicon Substances 0.000 claims description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 39
- 239000010408 film Substances 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 27
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 description 9
- 238000007254 oxidation reaction Methods 0.000 description 9
- 239000001257 hydrogen Substances 0.000 description 5
- 229910052739 hydrogen Inorganic materials 0.000 description 5
- 239000007790 solid phase Substances 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 238000001953 recrystallisation Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000001443 photoexcitation Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- -1 silicon ions Chemical class 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、絶縁基板上に形成される半導体装置の製造方
法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device formed on an insulating substrate.
絶縁膜上に結晶粒の大きな多結晶シリコン薄膜あるいは
、単結晶シリコン薄膜を形成する方法は、Ｓｏ工（５ｌ
ｉｃｏｎ Ｏｎ工ｎ５ｕｌａｔｏｒ ） 技術として
知られている。例えば、固相成長法、レーザービーム再
結晶化法などの方法がある。（参考文献応用物理 第５
４巻 第１２号 １２７４ページ、１９８５年）また、
固相成長法として、シリコン薄膜にシリコンイオンをイ
オン注入し、その後約６００℃程度の低温でアニールす
ると結晶成長するという方法も報告されている。（参考
文献。The method of forming a polycrystalline silicon thin film with large crystal grains or a single crystal silicon thin film on an insulating film is the So process (5L
It is known as On5lator technology. For example, there are methods such as solid phase growth method and laser beam recrystallization method. (References Applied Physics No. 5
(Volume 4, No. 12, Page 1274, 1985)
As a solid-phase growth method, a method has also been reported in which silicon ions are implanted into a silicon thin film and then annealed at a low temperature of about 600° C. to grow crystals. (References.
Ｊ、Ａｐｐｌ、 Ｐｈｙｓ、 ５９（７）、Ｉ Ａｐｒ
ｉｌ 、 ２４２２ページ １９８６年）
〔発明が解決しようとする課題〕
前記固相成長法においては、結晶成長の種となる核が、
多数存在する為に数多くの結晶粒が改長し該結晶粒のひ
とつひとつは大きく成長しない。J, Appl, Phys, 59(7), I Apr.
il, p. 2422, 1986) [Problem to be solved by the invention] In the solid phase growth method, the nucleus that becomes the seed for crystal growth is
Since there are a large number of crystal grains, many crystal grains are modified and each crystal grain does not grow large.
また、結晶粒がランダムに成長する為に、結晶粒界がど
こに存在するのかわからない。従って、このような従来
の方法で得られた多結晶シリ―ン膜を用いて薄膜トラン
ジスタを作製すると電気的特性のバラツキが大きく実用
化できない。例えば、結晶粒径の大きさが２μｒｒＬＩ
ｕ度に成長した多結晶シリコン薄膜にチャネル長１μｍ
の薄膜トランジスタを作製した場合を考える。従来の方
法では、これまで述べてきたように、結晶粒界がランダ
ムに存在する為に、基板上の場所によって、薄膜トラン
ジスタのチャネル内に結晶粒界が１個存在する場合と、
結晶粒界がまったく存在しない場合があり、この２つの
薄膜トランジスタの電気的特性はまったく異なる。一方
、レーザービーム再結晶化法においては、レーザービー
ムのくり返し走査が必要な為に大面積を一括して結晶成
長させる事はむずかしい。さらにレーザービーム内のエ
ネルギー分布をも制御する必要がある為大がかりで高価
な装置が要求される。Furthermore, since the crystal grains grow randomly, it is not known where the crystal grain boundaries exist. Therefore, if a thin film transistor is manufactured using a polycrystalline silicon film obtained by such a conventional method, the electrical characteristics will vary greatly and cannot be put to practical use. For example, the crystal grain size is 2μrrLI
Channel length of 1 μm in polycrystalline silicon thin film grown to U degree
Consider the case where a thin film transistor is fabricated. In the conventional method, as mentioned above, grain boundaries exist randomly, so depending on the location on the substrate, there may be one grain boundary within the channel of the thin film transistor, or there may be one grain boundary within the channel of the thin film transistor.
There may be no grain boundaries at all, and the electrical characteristics of the two thin film transistors are completely different. On the other hand, in the laser beam recrystallization method, repeated scanning of the laser beam is required, so it is difficult to grow crystals over a large area all at once. Furthermore, since it is necessary to control the energy distribution within the laser beam, large-scale and expensive equipment is required.
本発明は、上記のような従来のＳＯＩ法の問題点を解決
し、絶縁基板上の所定の位置に多結晶シリコンの結晶領
域を形成させ、該結晶領域内に薄膜トランジスタなどの
半導体装置を作製し、屯結晶シリコンを用いた場合と同
程度の特性の半導体装置を絶縁基板上でバラツキなく実
現する事を目的とする。非常に開港で安価な方法で上述
のような特性のすぐれたバラツキの少ない半導体装置を
実現する事を目的とする。The present invention solves the problems of the conventional SOI method as described above, forms a polycrystalline silicon crystal region at a predetermined position on an insulating substrate, and fabricates a semiconductor device such as a thin film transistor in the crystal region. The purpose is to realize a semiconductor device on an insulating substrate with characteristics comparable to those using crystalline silicon without any variation. The purpose of this invention is to realize a semiconductor device with excellent characteristics and little variation as described above using a very open and inexpensive method.
本発明の半導体装置の製造方法は、絶縁基板上に、シリ
コン薄膜を堆積させる第一の工程と、該シリコン薄膜上
に島状酸化膜あるいは島状窒化膜を形成する第二の工程
と、前記シリコン薄膜罠おいて、該島状０化膜におおわ
れていない領域を酸化させる第三の工程と、表面研磨し
て前記島状酸化膜の下のシリコン表面を露出させる第四
の工程と、非晶質シリコン薄膜を堆積させる第五の工程
と、前記第四の工程で露出されたシリコン表面を核とし
、前記非晶質シリコン薄膜を結晶化させて多結晶シリコ
ン薄膜を形成する第六の工程と、該多結晶シリコン薄膜
の結晶粒界部分を除く結晶領域内に半導体装置を形成す
る第七の工程を少なくとも有することを特做とする。The method for manufacturing a semiconductor device of the present invention includes a first step of depositing a silicon thin film on an insulating substrate, a second step of forming an island-like oxide film or an island-like nitride film on the silicon thin film, and the step of forming an island-like oxide film or an island-like nitride film on the silicon thin film. In the silicon thin film trap, a third step of oxidizing the region not covered with the island-like oxide film, a fourth step of surface polishing to expose the silicon surface under the island-like oxide film, and a non-oxidizing step. a fifth step of depositing a crystalline silicon thin film; and a sixth step of crystallizing the amorphous silicon thin film using the silicon surface exposed in the fourth step as a nucleus to form a polycrystalline silicon thin film. and a seventh step of forming a semiconductor device in a crystal region excluding a crystal grain boundary portion of the polycrystalline silicon thin film.
ここでは、アクティブマトリクス基板あるいは密着型イ
メージセンサ−などに本発明を用いた場合を例として本
発明の詳細な説明する。従って絶縁基板は可視光を透過
する透明性絶縁基板を用いる。第１図（α）において、
石英基板などの透明性絶縁基板１−１上に、シリコン薄
膜１−２を堆積させる。該シリコン薄膜１−２は結晶性
の良好な膜である事が望ましい。堆積方法としては、Ｅ
Ｂ蒸着法（Ｅｌｅｃｔｒｏｎ Ｂｅａｍ蒸着法）、スパ
ッタ法、 Ｍ Ｂ Ｅ （Ｍｏ１ｅｃｕｌａｒ Ｂｅａ
ｍ Ｋｐｉｔａｘｙ ）法、減圧ＯＶ Ｄ （Ｃｈｅｍ
ｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ ）法、
常圧ＣｖＤ法、プラズマＯＶＤ法、光励起ＣＶＤ法など
がある。堆積させたままでもよいが再結晶化させる為の
熱処理工程を入れてもよい。例えば、ＥＢ蒸着法やスパ
ッタ法やＭＢＺ法により堆積させられたシリコン薄膜は
、５００℃から７００℃の低温アニールにより結晶粒が
１〜２μｍに結晶成長する。また減圧ＣＶＤ法などで堆
積させられたシリコン薄膜は、シリコンイオン注入を行
ないシリコン薄膜を一担非晶質化させ、その後５００℃
から７００℃の低温アニールすると結晶粒が１〜２μｍ
に結晶成長する。またプラズマＣｖＤ法などで堆積させ
られたシリコン薄膜は、膜中に多量の水素を含んでいる
ので、３００℃から゛４５０℃程度のアニールで水素を
放出させ、その後５００℃から７００℃の低温アニール
で１〜２μｍの結晶粒に結晶成長させる。Here, the present invention will be explained in detail by taking as an example the case where the present invention is applied to an active matrix substrate, a contact type image sensor, or the like. Therefore, a transparent insulating substrate that transmits visible light is used as the insulating substrate. In Figure 1 (α),
A silicon thin film 1-2 is deposited on a transparent insulating substrate 1-1 such as a quartz substrate. The silicon thin film 1-2 is preferably a film with good crystallinity. As a deposition method, E
B evaporation method (Electron Beam evaporation method), sputtering method, MBE (Molecular Bea
m Kpitaxy) method, reduced pressure OV D (Chem
ical vapor deposition) method,
Examples include atmospheric pressure CVD method, plasma OVD method, and photoexcitation CVD method. It may be left as it is deposited, but a heat treatment step for recrystallization may be added. For example, in a silicon thin film deposited by EB evaporation, sputtering, or MBZ, crystal grains grow to 1 to 2 μm by low-temperature annealing at 500° C. to 700° C. In addition, silicon thin films deposited by low-pressure CVD method, etc. undergo silicon ion implantation to make the silicon thin film amorphous, and then heated at 500°C.
When annealed at a low temperature of 700°C, the grain size becomes 1-2 μm.
crystals grow. In addition, silicon thin films deposited by plasma CVD methods contain a large amount of hydrogen, so hydrogen is released by annealing at 300°C to 450°C, followed by low-temperature annealing at 500°C to 700°C. The crystals are grown into crystal grains of 1 to 2 μm in size.
このようにして得られたシリコン薄膜１−２上に島状酸
化膜１−５を形成する。例えば減圧ＣＶＤ法、常圧ＯＶ
Ｄ法、プラズマＯＶＤ法などの方法で前記シリコンＮ膜
１−２上に酸化膜（Ｓ１Ｏ，）を堆積させホトリソグラ
フィ法で該島状酸化＠１−６を形成する。酸化膜ではな
く窒化膜でもよいことはもちろんである。該島状酸化膜
１−５ひとつひとつの大きさ（以後ｔと呼ぶ）と、該島
状酸化膜間の距！（以後Ｘと呼ぶ）とは、本発明の目的
とする結晶性の良好な多結晶シリコン薄膜を作製する上
で重要なファクターとなるので以降必要に応じて説明す
る。概略を述べると、Ｌを１〜２μｍ、ｘを５０μｍ程
度となる。An island-shaped oxide film 1-5 is formed on the silicon thin film 1-2 thus obtained. For example, low pressure CVD method, normal pressure OV
An oxide film (S1O,) is deposited on the silicon N film 1-2 by a method such as the D method or a plasma OVD method, and the island-like oxide @1-6 is formed by a photolithography method. Of course, a nitride film may be used instead of an oxide film. The size of each island-like oxide film 1-5 (hereinafter referred to as t) and the distance between the island-like oxide films! (hereinafter referred to as X) is an important factor in producing a polycrystalline silicon thin film with good crystallinity, which is the object of the present invention, and will be explained below as necessary. Briefly, L is 1 to 2 μm, and x is approximately 50 μm.
次に熱酸化を行ない、前記シリコン薄膜１−２において
島状酸化膜１−６におおわれていない領域をすべて酸化
膜とする。このように形成された酸化膜をここではフィ
ールド酸化層１−４と呼ぶ。一方、シリコン薄膜１−２
において、島状酸化膜１−５におおわれていた領域は、
島状シリコン薄膜１−５として残る。前記フィールド酸
化層１−４の形成方法としては乾燥酸素中で７００℃か
ら１４００℃に加熱するａｒｙ 酸化法、酸化速度のよ
り速い方法としては水蒸気を導入して加熱するｙｅｔ
酸化法などの方法がある。これらの熱酸化は、フィー
ルド酸化層が透明性絶縁基板表面に達するまで行なう。Next, thermal oxidation is performed to convert all regions of the silicon thin film 1-2 that are not covered with the island-like oxide film 1-6 into an oxide film. The oxide film thus formed is herein referred to as field oxide layer 1-4. On the other hand, silicon thin film 1-2
In, the area covered with the island-like oxide film 1-5 is
It remains as an island-like silicon thin film 1-5. The method for forming the field oxide layer 1-4 is the ary oxidation method, which involves heating from 700°C to 1400°C in dry oxygen, and the yet method, which achieves a faster oxidation rate, involves introducing water vapor and heating.
There are methods such as oxidation method. These thermal oxidations are performed until the field oxidation layer reaches the surface of the transparent insulating substrate.
従って、この工程まで終了した基板はほぼ透明となって
おり、透明性絶縁基板として扱っても何ら問題はない。Therefore, the substrate completed up to this step is almost transparent, and there is no problem in handling it as a transparent insulating substrate.
また、島状酸化膜１−３の部分は、くぼんだ形状となっ
ている。Further, the portion of the island-like oxide film 1-3 has a concave shape.
一方、熱酸化工程は上述したように高温熱処理であ、る
ので、前記島状シリフン薄膜１−５は、前工程での状態
と比べてさらに結晶化が進んでいる。On the other hand, since the thermal oxidation process is a high-temperature heat treatment as described above, the island-shaped silicon thin film 1-5 is further crystallized compared to the state in the previous process.
続いて基板表面を表面研磨して、島状シリコン９膜１−
５の表面を露出させ、基板表面を平担にする。この工程
まで終了した時の基板の状態を第１図（ｄ）に示す。図
中１−６は研磨面を示す。Subsequently, the surface of the substrate is polished to form an island-shaped silicon 9 film 1-
The surface of No. 5 is exposed and the surface of the substrate is made flat. The state of the substrate upon completion of this step is shown in FIG. 1(d). In the figure, 1-6 indicates the polished surface.
表面は単結晶シリフンウェハの表面を鏡面研磨する場合
と同様な方法で研磨する。研磨面は不純物や欠陥が残ら
ないよ５に洗浄を必要に応じて行なう。The surface is polished in the same manner as mirror polishing the surface of a single crystal silicon wafer. The polished surface is cleaned as necessary to ensure that no impurities or defects remain.
次に非晶質シリコン薄膜１−７を堆積させる。Next, an amorphous silicon thin film 1-7 is deposited.
該非晶質シリコン薄膜１−７は、膜質が均一である事が
望ましい。堆積方法としては、前罠も述べたように、Ｋ
Ｂ蒸着法、スパッタ法、ＭＢＫ法。It is desirable that the amorphous silicon thin film 1-7 has uniform film quality. As for the deposition method, as mentioned above, K
B vapor deposition method, sputtering method, MBK method.
減圧ＯＶＤ法、常圧ＯＶＤ法、プラズマｃｖＤ法、光励
起ＯＶＤ法などの方法がある。いずれの方法においても
堆積温度を高くすると小さな結晶粒の存在する多結晶と
なってしまうので高くても６００℃以下としたほうがよ
い。水素が膜中に含まれないという点で、ＥＢ蒸着法、
スパッタ法２ＭＢＥ法などが有効である。その他の方法
で堆積し膜中に水素が含まれている場合は３５０℃から
４００℃の低温アニールで水素をゆっくりと放出させる
。There are methods such as a reduced pressure OVD method, a normal pressure OVD method, a plasma CVD method, and a photoexcitation OVD method. In either method, if the deposition temperature is increased, it will result in polycrystals with small crystal grains, so it is better to set the deposition temperature to 600° C. or less at most. The EB evaporation method, in that hydrogen is not included in the film,
Sputtering method, 2MBE method, etc. are effective. If the film is deposited by other methods and contains hydrogen, hydrogen is slowly released by low-temperature annealing at 350° C. to 400° C.
続いて、前記島状シリコン薄膜１−５を結晶成長の核と
して、該非晶質シリコン薄膜１−７を結晶成長させる。Subsequently, the amorphous silicon thin film 1-7 is grown using the island-shaped silicon thin film 1-5 as a nucleus for crystal growth.
前記島状シリコン薄膜１−５は、前に述べたように大き
さｔが１〜２μｍで、結晶粒径が１〜２μｍであるので
、該島状シリコン薄＠１−５には結晶粒界がまったく含
まれないか、あるいは多くても１個含まれるだけである
。結晶成長は島状シリコン薄膜１−５に重なっている部
分を中心として放射状にすすむ。そして島状シリフン薄
膜１−５間の中間点で両方向から成長してきた結晶粒が
ぶつかり合い、結晶粒界１−８が生じる。結晶粒の成長
は１００μｍ程度に達する。The island-shaped silicon thin film 1-5 has a size t of 1 to 2 μm and a crystal grain size of 1 to 2 μm, as described above, so that the island-shaped silicon thin film 1-5 has a crystal grain boundary. Either there are none, or there is at most one. Crystal growth progresses radially centering on the portion overlapping the island-shaped silicon thin film 1-5. Then, at the midpoint between the island-shaped silicon thin films 1-5, the crystal grains grown from both directions collide with each other to form a crystal grain boundary 1-8. The growth of crystal grains reaches about 100 μm.
従って前記島状シリコン薄膜１−５の間の距離Ｘを１０
０μ罵以下にしておけば、前記島状シリコン薄膜１−５
と結晶粒界１−８との間の領域は完全な結晶領域１−９
となる。結晶粒の成長が１゜０μｍ以上に達成される場
合にはＸをさらに大きくする事ができ、より大きな結晶
領域を実現できる。結晶成長の方法は、５００℃から７
００１）の低温アニールで、前記島状シリコン薄膜１−
５を核として結晶成長させる。一種の固相エピタキシャ
ル成長といつこともできる。非晶質シリコン薄膜１−７
を堆積させた状態で結晶成長させてもよいが、該非晶質
シリコン薄膜１−７上に酸化膜などをキャッピングして
から結晶成長させる事も考えられる。この場合は結晶領
域１−９の表面の平担性を保つ点で効果がある。もちろ
ん結晶成長後、該酸化膜は除去してもよいし、あるいは
その後作製する半導体装置の一部として利用してもよい
。Therefore, the distance X between the island-shaped silicon thin films 1-5 is set to 10
If it is kept below 0μ, the island-shaped silicon thin film 1-5
The region between and grain boundary 1-8 is a complete crystal region 1-9
becomes. If crystal grain growth is achieved to 1°0 μm or more, X can be further increased, and a larger crystal region can be realized. The method of crystal growth is from 500℃ to 7
001), the island-shaped silicon thin film 1-
Crystals are grown using 5 as a nucleus. It can always be referred to as a type of solid-phase epitaxial growth. Amorphous silicon thin film 1-7
Although the crystal may be grown in the state in which the amorphous silicon thin film 1-7 is deposited, it is also possible to grow the crystal after capping the amorphous silicon thin film 1-7 with an oxide film or the like. In this case, it is effective in maintaining the flatness of the surface of the crystal region 1-9. Of course, after the crystal growth, the oxide film may be removed, or it may be used as part of a semiconductor device to be manufactured later.
基板表面は平担なので結晶成長は一様に進行するこのよ
うにして島状シリコン薄膜１−５と結晶粒界１−８との
間に形成された結晶領域１−９の部分を利用して半導体
装置を作製する。核となる島状シリコン薄膜１−５には
多くても１個の結晶粒界しか含まれないので、本発明に
おいて半導体装置を作製する点において何ら問題になら
ない。Since the substrate surface is flat, crystal growth progresses uniformly.Using the crystal region 1-9 formed between the island-like silicon thin film 1-5 and the crystal grain boundary 1-8 in this way, Fabricate a semiconductor device. Since the island-shaped silicon thin film 1-5 serving as the core contains at most one crystal grain boundary, there is no problem in manufacturing a semiconductor device in the present invention.
本実施例においては薄膜トランジスタを作製する場合を
例として説明する。結晶領域１−９の中にホトリソグラ
フィ法により単結晶能動領域１−１０をパターニングし
、続いてゲー）酸化［１−１１を形成する。ゲート酸化
膜は熱酸化法で形成する。その後多結晶シリコンなどで
ゲート電１ｉ１１．−１２を形成し該ゲート電極１−１
２をマスクとして、ソース及びドレイン領域１−１５を
形成する。Ｐチャネルの場合はＢ（ポロン）、Ｎチャネ
ルの場合は、Ｐ（’Ｉン）ＩＡＥＩ（ヒ素）を不純物添
加する。添加方法としてはイオン注入法あるいは拡散法
などがある。次に眉間絶縁膜１−１４として酸化膜ある
いは窒化膜を堆積させ、コンタクトホールを形成して金
属電極１−１５を形成する。In this embodiment, a case where a thin film transistor is manufactured will be described as an example. A single-crystal active region 1-10 is patterned in the crystal region 1-9 by photolithography, followed by formation of a Ga) oxide [1-11]. The gate oxide film is formed by a thermal oxidation method. After that, gate electrodes 1i11. -12 and the gate electrode 1-1
2 as a mask, source and drain regions 1-15 are formed. In the case of a P channel, B (poron) is added as an impurity, and in the case of an N channel, P ('In)IAEI (arsenic) is added as an impurity. Addition methods include ion implantation, diffusion, and the like. Next, an oxide film or a nitride film is deposited as the glabellar insulating film 1-14, contact holes are formed, and metal electrodes 1-15 are formed.
実施例では薄膜トランジスタの場合を例にとって゛説明
したが、バイポーラ型トランジスタなどその他の半導体
装置にももちろん応用することができる。Although the embodiments have been described using a thin film transistor as an example, the present invention can of course be applied to other semiconductor devices such as bipolar transistors.
種結晶の上に非晶質シリコン薄膜を堆積し、該非晶質シ
リコン薄膜を低温で固相成長させることができるので絶
縁基板、特に石英基板のような透明性絶縁基板上にほぼ
単結晶に近いシリコン薄膜を作製することができる。種
結晶となる島状シリコン薄膜が形成された表面が基板全
面にわたって平担となっているので、形状による結晶成
長のムラについてはまったく問題とならない。従って、
その上に堆積させられた非晶質シリコン薄膜の結晶成長
は非常に均一に進行する。結晶粒界の位置及び結晶領域
の位置を基板上所定の場所に形成することができるので
、結晶領域のみを用いて半導体装置を作製することがで
き、嘔結晶シリコン薄膜を用いた半導体装置と同等の特
性が得られる。An amorphous silicon thin film is deposited on a seed crystal, and the amorphous silicon thin film can be grown in solid phase at a low temperature, so it can be grown almost like a single crystal on an insulating substrate, especially a transparent insulating substrate such as a quartz substrate. Silicon thin films can be produced. Since the surface on which the island-shaped silicon thin film serving as the seed crystal is formed is flat over the entire surface of the substrate, there is no problem with uneven crystal growth due to shape. Therefore,
Crystal growth of the amorphous silicon thin film deposited thereon proceeds very uniformly. Since the positions of crystal grain boundaries and crystal regions can be formed at predetermined locations on the substrate, it is possible to fabricate semiconductor devices using only crystal regions, which is equivalent to semiconductor devices using crystalline silicon thin films. The following characteristics are obtained.
本発明を薄膜トランジスタに応用すれば、ドライバー回
路を同一基板内に作り込んだアクティブマ） ＩＪクス
基板の高速化が実現できろ。さらに電源電圧の低減、消
費電流の低減、信頼性の向上に関しても大きな効果があ
る。If the present invention is applied to thin film transistors, it will be possible to realize high-speed IJ substrates with driver circuits built into the same substrate. Furthermore, there are significant effects in reducing power supply voltage, reducing current consumption, and improving reliability.
本発明を、光電変換素子とその走査回路を同一チップ内
に集積し・た密着型イメージセンサ−に応用した場合に
は、読み取り速度の高速化、高解像度化、及び階調を取
る場合に非常に大きな効果を生み出す。電源電圧の低減
、消費電流の低減、信頼性の向上にも効果は大きい。高
解像度化が達成されるとカラー読み取シ用密着型イメー
ジセンサ−への応用も容易となる。When the present invention is applied to a contact image sensor in which a photoelectric conversion element and its scanning circuit are integrated on the same chip, it is possible to achieve an extremely high reading speed, high resolution, and gradation. produces a great effect. It is also highly effective in reducing power supply voltage, reducing current consumption, and improving reliability. Once high resolution is achieved, it will be easier to apply it to a contact type image sensor for color reading.
レーザービーム照射装置などの精巧で高価な装置を心安
としないので、作製が簡単であり、費用の低減化に役だ
つ。Since it does not require sophisticated and expensive equipment such as laser beam irradiation equipment, it is easy to manufacture and is useful for reducing costs.
以上述べたように、本発劣は、絶縁基板特に透明性絶縁
基板上に単結晶シリコン薄膜を作製する場合に、非常に
有効なものである。As described above, this oxidation defect is very effective when producing a single crystal silicon thin film on an insulating substrate, especially a transparent insulating substrate.
第１図（α）から（！りは、本発明における半導体装置
の製造方法を示す工程図である。
１−３・・・・・・島状酸化膜
１−４・・・・・・フィールド酸化層
１−５・・・・・・島状シリコン薄膜
１−６・・・・−・研磨面
１−８・・・・・・結晶粒界
１−９・・・・・・結晶領域
以上
出願人 セイコーエプソン株式会社
ｔｂ）Ｉ−１
（Ｃ）
（＋ンFIGS. 1(α) to (!) are process diagrams showing the method for manufacturing a semiconductor device according to the present invention. 1-3... Island-shaped oxide film 1-4... Field Oxide layer 1-5... Island silicon thin film 1-6... Polished surface 1-8... Grain boundary 1-9... Crystal region or above Applicant Seiko Epson Corporation tb) I-1 (C) (+n
Claims (1)
と、該シリコン薄膜上に島状酸化膜あるいは島状窒化膜
を形成する第二の工程と、前記シリコン薄膜において、
該島状酸化膜におおわれていない領域を酸化させる第三
の工程と、表面研磨して前記島状酸化膜の下のシリコン
表面を露出させる第四の工程と、非晶質シリコン薄膜を
堆積させる第五の工程と、前記第四の工程で露出された
シリコン表面を核とし、前記非晶質シリコン薄膜を結晶
成長させて多結晶シリコン薄膜を形成する第六の工程と
、該多結晶シリコン薄膜の結晶粒界部分を除く結晶領域
内に半導体装置を形成する第七の工程を少なくとも有す
ることを特徴とする半導体装置の製造方法。A first step of depositing a silicon thin film on an insulating substrate, a second step of forming an island-like oxide film or an island-like nitride film on the silicon thin film, and in the silicon thin film,
a third step of oxidizing the region not covered with the island-like oxide film; a fourth step of surface polishing to expose the silicon surface under the island-like oxide film; and depositing an amorphous silicon thin film. a fifth step; a sixth step of forming a polycrystalline silicon thin film by crystal-growing the amorphous silicon thin film using the silicon surface exposed in the fourth step as a core; A method for manufacturing a semiconductor device, comprising at least a seventh step of forming a semiconductor device in a crystal region excluding a crystal grain boundary portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63040100A JP2687394B2 (en) | 1988-02-23 | 1988-02-23 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63040100A JP2687394B2 (en) | 1988-02-23 | 1988-02-23 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01214111A true JPH01214111A (en) | 1989-08-28 |
| JP2687394B2 JP2687394B2 (en) | 1997-12-08 |
Family
ID=12571446
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63040100A Expired - Fee Related JP2687394B2 (en) | 1988-02-23 | 1988-02-23 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2687394B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02252736A (en) * | 1989-03-28 | 1990-10-11 | Ube Ind Ltd | Silicon-containing polycyclic aromatic polymer and its production |
| JPH02274732A (en) * | 1989-04-18 | 1990-11-08 | Ube Ind Ltd | Silicon-containing polycyclic aromatic polymer and its production |
-
1988
- 1988-02-23 JP JP63040100A patent/JP2687394B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02252736A (en) * | 1989-03-28 | 1990-10-11 | Ube Ind Ltd | Silicon-containing polycyclic aromatic polymer and its production |
| JPH02274732A (en) * | 1989-04-18 | 1990-11-08 | Ube Ind Ltd | Silicon-containing polycyclic aromatic polymer and its production |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2687394B2 (en) | 1997-12-08 |
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