JPH01214945A - Microcomputer - Google Patents

Abstract

PURPOSE:To efficiently utilize a terminal by comparing output data with the data read out by a data reading-out means in accordance with an output data monitoring instruction and, when they do not coincide with each other, outputting an interruption requesting signal. CONSTITUTION:When a monitoring instruction executing means 22 reads instruction words which instructs monitoring of output data, the means 22 allows an arithmetic means to read the data to be outputted to a readout means 24 and the data actually outputted to the terminal 36 of the output data written in monitoring means 23 and 23 and, when they are coincident, discriminates it as normal. When they are discordant, the means 22 discriminates it as abnormal and allows an interruption control circuit 40 to output an interruption requesting signal. Therefore, the output data can be monitored without using any terminal other than the terminal 36 through which the data are outputted and terminals limited in number can be utilized efficiently.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a central processing unit, a program memory, an interrupt control circuit, a storage means into which output data is written under the control of the central processing unit, and a storage means. The present invention relates to a microcomputer having output means for inputting output data written in a terminal and outputting it to a terminal.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional example of this type of microcomputer, and FIG. 5 shows how the microcomputer 50 shown in FIG. 4 connects the input/output terminals 53, .
It is an explanatory view showing whether ~536 is used.

The microcomputer 50 includes a program memory 51,
CPU52. It has an input/output device 539 and an interrupt control circuit 54. The CPU 52 calculates various data based on the contents of the program memory 51. The CPU 52 controls the input/output device 53 via the control bus and address bus, and sends and receives data via the data bus. The interrupt control circuit 54 performs interrupt control for the CPU 52. The input/output device 53 is controlled by the CPU 52 and is connected to an external device 60 through an output terminal 53 . , 532.533 via data D, ,D
2. D3 and the output data D, , D2 . Input terminals 534, 535.5 for self-checking D3
36.

Data D+, D2, D3 input from input terminals 534, 53s, 536 are output terminals 53+, 5.
32, 533 output data l), , D2. D
3, and if they are the same, it is normal, and if they are different, it is detected that an abnormality has occurred. Therefore, the output data D, , D2 of the microcomputer 50.

This allows monitoring of the logic level of D3.

[Problem to be solved by the invention]

The conventional microcomputer described above has an input/output device 5.
3 output terminal 53. , 532.533 output data D, , D2. In order to monitor D3, the output data D, , D2 . Since D3 is input to the input terminals 534, 535, 536, the input terminals 534, 535, 536 cannot be used for other purposes, and the limited number of terminals cannot be used efficiently.

[Means to solve the problem]

The microcomputer of the present invention includes an output data reading means for independently reading out the output data written in the storage means and the data output from the output end of the output means based on an output data monitoring instruction, and a program. When a command word instructing to monitor output data is read from the memory, the output data monitoring instruction is output to the output data reading means, and the calculation means of the central processing unit compares both data read by the output data reading means, and detects a discrepancy. and a monitoring instruction execution means for instructing the interrupt control circuit to output an interrupt request signal when the interrupt request signal is detected.

[Effect]

In this way, when the monitoring command execution means reads a command instructing to monitor output data, the output data reading means reads the data to be output and the data actually output to the terminal, respectively. If the data match, it is determined to be normal, and if they do not match, it is determined to be abnormal, and the interrupt control circuit outputs an interrupt request signal.・Output data can be monitored without any need. , (Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a microcomputer according to the present invention, and FIG. 2 is a timing chart showing the operation of the embodiment of FIG.

The microcomputer of this embodiment includes a program memory 10, a central processing unit 20 (hereinafter referred to as CPU 20), an input/output device 30, and an interrupt control circuit 40.

The CPU 20 uses an address bus 211. data bus 212,
Instruction register 22. Instruction decoder 24. Temporary register 23. , 232. Arithmetic and logic unit 25 (hereinafter referred to as ALU 25), result storage register 261, flag register 262. Inverter 27. AND circuit 28.
It has a timing control circuit 29.

The instruction register 22 reads the instruction word from the program memory IO, and based on the read instruction word, the instruction register 22 reads the instruction word from the address bus 21.
The address is outputted to the instruction decoder 24 as an instruction. The timing control circuit 29 receives clocks φ and φ, which are two-phase signals.
2 and instruction execution timing Tl, T2. T3. T
Outputs 4. The instruction decoder 24 decodes the input instruction and determines the instruction execution timings T, , T7 . T3. Lead in synchronization with T4.

Control signals RD and WR for instructing write and temporary register 23. , 232 is output, and when an interrupt signal REQ is received, the interrupt is accepted. Temporary register 23, , 2
32 are respective timings T1φ2. In synchronization with T2φ2, the data sent from the input/output device 30 is transferred to the data bus 2.
1. Read from. When the ALU 25 does not receive the control signal A, it inputs the data held in the temporary registers 23, 232, performs calculations, and outputs the calculation results to the result storage register 261. Also, when the control signal A is being input, the temporary register 23. , 23
Compare the data held by □ and store the comparison result in the result storage register 26. If the two compared data match, the flag register 262 is set to logic 1, and if they do not match, the flag register 262 is set to logic 0. As a result, the register 26 outputs the data input from the ALU 25 to the data bus 212 in synchronization with timing T3φ2.

The flag register 262 receives timing T3 from the ALU 25.
A logic 0 or logic 1 set in synchronization with φ2 is outputted via the inverter 27. The AND circuit 28 ANDs the control signal A, the instruction execution timing T4, and the output of the inverter 27. When the interrupt control circuit 40 receives a logic 1 from the AND circuit 28, it outputs an interrupt request signal REQ to the instruction decoder 24.

The input/output device 30 includes an address decoder 31 . Output latch 32. AND circuit 33□, 332.333.334° buffer circuit 341, 342, 343, terminal 36
has. Although the input/output device 3o actually has a plurality of input devices and output devices for bits, in this embodiment, only an output device for one bit is shown to simplify the explanation.

Address decoder 31 outputs logic 1 if the address input from address bus 211 selects output latch 32 . AND circuit 33. is the control signal WR
, the clock φ2, and the output of the address decoder 31 are ANDed. The output latch 32 is an AND circuit 33. 1 of the connected data bus 212 when the output of
Latch the bit. Buffer circuit 34. inputs the output of the output latch 32 and outputs it to the terminal 36. The AND circuit 332 ANDs the control signal A and the instruction execution timing TI. The AND circuit 333 ANDs the jlIIJ control signal RD, the instruction execution timing T, and the output of the address decoder 31. The OR circuit 35 ORs the output of the AND circuit 332 and the output of the AND circuit 333. The buffer circuit 34 outputs the output of the output latch 32 to the data bus 212 when the output of the OR circuit 35 is logic 1. The AND circuit 334 ANDs the control signal A and the instruction execution timing T2. The buffer circuit 343 is an AND circuit 33
When the output of the terminal 4 is logic 1, the logic level of the terminal 36 is inputted and output to the data bus 212.

Next, the operation of this embodiment will be explained with reference to FIG.

When the microcomputer is executing instructions according to the program and instruction words stored in the memory 10, if one of the instruction words instructs a check instruction for the output data of the output latch 32, that instruction word is input. The instruction register 22 outputs an address addressed to the address decoder 31 and outputs a check instruction to the instruction decoder 24. The instruction decoder sets control signals RD, WR, and A to logic 1 and 0.1, respectively, at instruction execution timing T. Since the output of the AND circuit 331 is set to logic 0 by the control signal WH, the output latch 32 holds the output latched immediately before. Command execution timing T! In this case, the outputs of AND circuits 332 and 333 are logic 1, and the output of AND circuit 334 is logic 0. Since the output of the OR circuit 35 also becomes logic 1, the buffer circuit 342 becomes active and transfers the output held by the output latch 32 to the data bus 21.
Output to 2. The data of the output latch 32 output to the data bus 212 is stored in the temporary register 23. when the clock φ2 is logic 1 at the instruction execution timing T1. is read into. At instruction execution timing T2, the outputs of the AND circuits 332 and 333 become logic O, so the output of the OR circuit 35 also becomes logic 0, and the buffer circuit 342 becomes inactive. Since the output of the AND circuit 334 becomes logic 1, the buffer circuit 343 becomes active, and the data at the terminal 36 is output to the data bus 212. The output data of the terminal 36 is read into the temporary register 232 in synchronization with timing T2φ2. At instruction execution timing T3, the ALU 25 stores the temporary register 23. ,． 232, and the comparison result is stored in the result storage register 26. is held in synchronization with timing T3φ2, and if the compared data match, the logic becomes 1.
However, if they do not match, a logic 0 is held in the flag register 262 in synchronization with timing T3φ2. When a logic 0 is held in the flag register 262, a logic 1 is output from the AND circuit 28 at instruction execution timing T4, so an interrupt request signal REQ is output from the interrupt control circuit 40, indicating that an abnormality has occurred in the output data. is detected.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

Since this embodiment differs from the first embodiment only in the input/output device 39, the explanation will mainly be given to the input/output device 39, which is different from the input/output device 30 of the first embodiment. Circuits designated by the same reference numerals as in the first embodiment operate in the same manner as in the first embodiment, and therefore their explanation will be omitted.

The AND circuit 33° receives the output of the address decoder 31 for selecting the PM clutch 7, the control signal WR, and the clock φ2.
Take the AND with. The PM clutch 7 inputs the data on the data bus 212 when the output of the AND circuit 33° is logic 1, holds the input data when the output of the AND circuit 33° is logic O, and changes the logic of the held data. Invert and output. AND - circuit 335 is address decoder 3
1 selects the output latch 32, the command execution timing T, the control signal RD, and the output of the PM clutch 7, and performs an OR circuit 35.1. takes the OR of the output of the AND circuit 332 and the output of the AND circuit 335. The inverter 38 inverts the logic of the output of the PM clutch 7. The AND circuit 336 outputs the address decoder 31 from the output latch 3.
The selection output for selecting 2, the output of the inverter 38, and the control signal RD are ANDed. The OR circuit 352 takes the OR of the AND circuits 334 and 336. The buffer circuit 34° becomes high impedance when the output of the PM clutch 7 is logic 0, and when it is logic 1, it operates in the same way as the buffer circuit 34°.

Next, the operation of the input/output device 39 of this embodiment will be explained.

When the address decoder 31 receives an address for selecting the PM clutch 7, it outputs a logic 1 to the AND circuit 33°. The AND circuit 33° that inputs this output outputs the control signal WR.
When we AND the clock φ2 and output a logic 1, we get
PM clutch 7 inputs data output to data bus 212 .

(1) When PM clutch 7 is set to logic 0.

The buffer circuit 34o and the AND circuit 335 become active, and the AND circuit 336 becomes inactive, forming the same output port as the input/output device 30 of the first embodiment, so a description thereof will be omitted.

(2) When PM clutch 7 is set to logic 1.

The buffer circuit 34o becomes high impedance, the AND circuit 335 becomes inactive, and the AND circuit 336 becomes active. Therefore, it serves as an input port that reads data from the terminal 36 via the buffer circuit 343 under the control of the control signal RD.

In the second embodiment, the logic set to the PM clutch 7 allows
When used as an output port, it can be similar to the first embodiment and can also be used as an input port, making it possible to use the limited number of terminals 36 more flexibly. Further, in order to realize this, the PM clutch 7. is substantially increased from the first embodiment. AND circuit 33o, inverter 38. There is only an OR circuit 352.

〔Effect of the invention〕

As explained above, in the present invention, when the monitoring command execution means reads the command word instructing the monitoring of output data, the data to be output to the output data reading means and the data actually output to the terminal are read respectively. If the read data match, it is determined to be normal, and if they do not match, it is determined to be abnormal, and the interrupt control circuit outputs an interrupt request signal. Since output data can be monitored without using any terminals, the limited number of terminals can be used efficiently.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing a first embodiment of the microcomputer of the present invention, FIG. 2 is a timing chart showing the operation of the embodiment of FIG. 1, and FIG. 3 is a diagram of the present invention. Fig. 4 is a block diagram showing a conventional microcomputer, and Fig. 5 shows how the microcomputer shown in Fig. 4 uses input/output terminals to check output data. FIG. lO...Program memory, 20...-CPU. 21, Address bus, 2I2, Data bus, 22, Instruction register, 23+, 2:12, Temporary register, 24, Instruction decoder, 25 ...ALU, 26, ...Result storage register, 262--Flag register, 27-----Inverter, 2a-----AND circuit, 29-------- -Timing control circuit, 3Q, 39-
...Input/output device, 31...Address decoder, 32...Output latch, 33°, 33. , ~. 336...AND circuit, 34°, 34. , 34. ．． 343...Buffer circuit, 35, 351, 352...OR circuit, 36...Terminal, 37-...PM latch, 38... Inverter, 10... Interrupt 1b control circuit.

Claims (1)

[Scope of Claims] 1. A central processing unit, a program memory, an interrupt control circuit, a storage means into which output data is written under the control of the central processing unit, and an input device for inputting the output data written in the storage means. , a microcomputer having an output means for outputting to a terminal, the output data written in the storage means and the data output from the output terminal of the output means are independently input based on an output data monitoring instruction. an output data reading means to read out; and upon reading a command word instructing monitoring of output data from the program memory, outputting an output data monitoring instruction to the output data reading means, and reading out both data read by the output data reading means; 1. A microcomputer comprising: a monitoring command execution means for making a comparison with an arithmetic means of a central processing unit and instructing the interrupt control circuit to output an interrupt request signal when a discrepancy is detected.