JPH01215111A - Transversal equalizer - Google Patents

Abstract

PURPOSE:To eliminate the need for adjustment inexpensively by adopting a strip line for a delay line of a transversal filter part. CONSTITUTION:An IF band input signal Si receiving orthogonal amplitude modulation is subject to output level control by an automatic gain control signal ca by a variable gain circuit 10 to form a signal Sa. The signal Sa is retarded by delay circuits (delay time T) 11, 12 using a strip line, and signals Sa-Sc are extracted via three taps. Since the strip line is used for the delay line of the transversal filter, the transversal type equalizer with ease of adjustment is obtained inexpensively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic equalizer using a transversal filter.

[Conventional technology]

In digital wireless transmission systems, line quality deteriorates due to waveform distortion due to multi-band sphaging that occurs in the propagation path, but it is known that this can be improved by applying a transversal filter type equalizer. There is.

The delay line of the transversal filter section of a conventional transversal equalizer is as shown in FIG.

It consists of a three-stage all-pass type circuit consisting of a coil and a capacitor.

FIG. 4 shows an example of a conventional transversal equalizer. In FIG. 4, an IF band large input signal Si subjected to quadrature amplitude modulation first becomes a signal S whose output level is controlled by an automatic gain control signal section in a variable gain circuit 10. Signal S
A is delayed in delay circuits (delay time T) 13 and 14 using an LCC all-pass network shown in FIG. 3, and signals s, , Sb, and Sc are taken out through three taps. Of these, the signals Sa and S are variable weighting circuits 101 and 1 constituting the variable layering circuit group on the in-phase side, respectively.
03. The variable weighting circuits 101 and 103 are.

Tap weights are controlled by tap control signals Wd and cf, respectively, and signals sd e Sf are output. at the same time.

Signals Sa and Sc are applied to variable weighting circuits 102 and 104, respectively, forming a group of variable weighting circuits on the orthogonal side. The variable weighting circuits 102 and 104 have tap weights controlled by tap control signals ell and eg, respectively, and output signals Se and Sg.

Among the signals output from the above variable weighting circuit group,
The signal 5dpSf is combined with the main tap signal Sb by the in-phase side signal combining circuit 111. On the other hand, signal S. , Sg are synthesized by the orthogonal side signal synthesis circuit 112. Each output signal S of these two signal synthesis circuits 111 and 112
h and Sj are vector-combined so as to be orthogonal to each other in a 90° directional coupler 113, and are output to a demodulator along with the IF band signal Sk, which is equalized by 9.

The control signal generation circuit 20 receives error signals EP, EQ and a quadrant determination signal DP input from the demodulator.

DQ is used to generate control signals ca'*cd' to Cg'.

These control signals (!a' @ cd's C8'*Cf
' and Cg' are input to the initial value setting circuit 30, and when the 2 equalizer is in a divergent state, ca=1, cd=ce=c
The initial value is set to f=cg=:O, and this state is maintained until carrier synchronization of the demodulator is established. After carrier synchronization is established, control signal ca is sent.

cd, ce, cf and cg are respectively the same as the control signals ca'+cd'ce', cf' and Cg', and the transformer equalizer enters the equalization state.

[Problem to be solved by the invention]

In the conventional transversal equalizer mentioned above,
All-pass circuits made up of coils and capacitors used as delay circuits are expensive. Further, since adjustment is time consuming and difficult, it has the disadvantage that it is not suitable for mass production.

An object of the present invention is to eliminate the drawbacks of the conventional transversal equalizers described above and to provide a transversal equalizer that is inexpensive and easy to adjust.

[Means to solve the problem]

The transversal equalizer according to the present invention is characterized in that a strip line is used for the delay line of the transversal filter section.

〔Example〕

As shown in FIG. 2, the strip line has four conductive turns printed on a ceramic substrate, and a signal passes through these conductive mother turns to obtain a delay amount.

The formula for calculating the amount of delay is as follows: Let D be the amount of delay.

It is expressed as Here, L is the length of four turns of the board.

η represents the shortening rate of spatial wavelength, and C represents the speed of light, and in the case of a ceramic substrate, η = 0.37.

As can be seen from the above-mentioned strip line manufacturing method, strip lines can be made by simply printing the arm turns on a ceramic substrate, and do not require complicated adjustments.
It can be mass-produced easily and inexpensively.

FIG. 1 is a block diagram of another embodiment of the present invention.

IF large input signal S1. that has undergone quadrature amplitude modulation. First, the output voltage of the variable gain circuit 10 is controlled by the automatic gain control signal ea, resulting in a signal S3. The signal Sa is.

Delay circuit using strip line (delay time T) 11
and 12, and the signal S
a, Sb, and Sc are extracted. Of these, signals Sa, S
c is applied to variable weighting circuits 101 and 103, respectively, forming a group of variable weighting circuits on the in-phase side. The variable weighting circuits 101 and 103 are.

Each tap weight is controlled by a tap control signal cd@cf, and signals Sd and Bf are output. at the same time.

The signals Sa and Sc are each a variable weighting circuit on the orthogonal side.
The signal is applied to variable weight receiving circuits 102 and 104 forming the path group. The variable weighting circuits 102 and 104 each have
The tap weights are controlled by tap control signals ee, eg, and the signal S. Output tag.

Among the signals output from the above variable weighting circuit group,
The signal 5deSf is combined with the main tap signal sb by the in-phase side signal combining circuit 111. On the other hand, signal S. , Sg are synthesized by the orthogonal side signal synthesis circuit 112. The respective output signals 8 of these two signal synthesis circuits 111 and 112
h and Sj are vector-combined so as to be orthogonal to each other in the 9o0 direction generator 113, and become an equalized IF' band signal sk, which is output to the demodulator.

The control signal generation circuit 20 generates control signals ca', cd'-cg' using error signals EP, EQ and quadrant determination signals DP, DQ input from the demodulator. These control signals ca', cd', ce', cf' and cg'
is input to the initial value setting circuit 30, and when the equalizer is in a divergent state, it is set to the initial value ca=1, cd=ca=cf=cg=o, and this value is maintained until carrier synchronization of the demodulator is established. maintain condition. After carrier synchronization is established, the control signal ca@
Cd1C1epcf and cg/d, respectively, the control signals ea'e cd'.

ea', cf' and cg' are the same, and the transversal equalizer enters the equalization state.

Comparing the embodiment of the present invention shown in FIG. 1 with the conventional example shown in FIG. 4, they have exactly the same configuration except for the delay circuits 13 and 14. That is, while the delay circuits 11.12 in FIG. 1 use strip lines, the delay circuits 13.12 in FIG.
14 is a three-stage all-pass type circuit consisting of a coil and a capacitor.

Therefore, it has equalization capabilities such as the IP type transversal equalizer of the present invention and the conventional IF' type transversal equalizer.

〔Effect of the invention〕

As explained above, the present invention uses a strip line as the delay line of the transversal filter section, thereby making it inexpensive and requiring no adjustment.

It has the effect of producing great scenery.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an IF type transversal equalizer using the stripline of the present invention, and FIG. 2 is a configuration diagram of the stripline used in the delay section of the transversal filter according to the present invention. , FIG. 3 is a circuit diagram of a three-stage all-pass type consisting of a coil and a capacitor used in the delay section of a conventional transversal filter, and FIG. 4 is a block diagram of a conventional IF type transversal equalizer. 11.12 is a stripline type delay circuit. 13 and 14 are LC type delay circuits, and 101 to 104 are variable weighting circuits.

Claims (1)

[Claims] 1. An automatic gain control circuit that receives an input signal and keeps the output constant, a tapped delay line that receives the output of the automatic gain control circuit as an input, and an in-phase side and an in-phase side connected to each tap of the tapped delay line. A variable weighting circuit on the orthogonal side, a signal synthesis circuit on the in-phase side that receives the output of the variable weighting circuit on the in-phase side as input, and a signal synthesis circuit on the orthogonal side that receives the output of the variable weighting circuit on the orthogonal side as input. a transversal filter section comprising a circuit and a 90° directional coupler inputting the outputs of the in-phase side and quadrature side signal synthesis circuits, and an error signal from a demodulator cascade-connected to the transversal filter section; An IF type transversal equalizer comprising a control signal generation circuit that receives a quadrant signal and generates an automatic gain control signal and a tap control signal, wherein the delay line is a strip line. Maker.