JPH012155A - External storage device write control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a write control method for an external storage device in a computer system, and in particular, when an external storage device is controlled using a control device with a cache memory, The present invention relates to a write control method suitable for improving the performance of write processing of an external storage device.

[Conventional technology]

2. Description of the Related Art In order to improve the performance of an external storage device such as a disk storage device in a computer system, a control device with a cache memory, which has a cache memory configured from a semiconductor memory within the control device, is widely used.

Frequently used data is stored in this cache memory, and in response to a command to read the data from the host device, the data is read from the cache memory and transferred to the host device without reading from the external storage device. Access is possible within the access time of semiconductor memory, enabling high-speed data processing. Generally, the access time of a disk storage device is several tens of milliseconds, whereas the access time of a semiconductor memory is several hundred nanoseconds.

There is a difference of about 105.

As described above, the conventional control device with a cache memory can realize high-speed reading processing from an external storage device. However, when it comes to writing to external storage devices,
At present, no efforts have been made to improve performance.

In addition, as a prior art related to the present invention, Japanese Patent Application Laid-open No. 1983-
There is an invention disclosed in Japanese Patent No. 135563. [Problems to be Solved by the Invention] In the prior art, the reason why a control device with a cache memory cannot speed up the write processing is due to the following reason. In other words, if the write data from the host device is written to the cache memory once and then written to the external storage device using free time, the performance of the write processing will improve, but the data will not be written to the external storage device. This is because if a failure occurs in the cache memory section or control device beforehand, the written data will be lost, which will pose a reliability problem.

The present invention has been made in view of the problems of the prior art described above, and is a write control method for an external storage device that speeds up the writing process to the external storage device and also maintains the reliability of the written data. is intended to provide.

[Means for solving problems]

In the external storage device write control method of the present invention, when data sent from a host device is written to the external storage device, data that is easy to reproduce is once stored in a cache memory and then written to the external storage device.

Data that is difficult to reproduce is characterized by being written to both the cache memory and the external storage device at the same time.

[Effect]

According to the present invention, data having attributes that are easy to reproduce are temporarily stored in the cache memory and then written to the external storage device.
Even if a failure occurs in the control device etc. and the data in the cache memory is lost before being written to the external storage device,
Since it can be easily reproduced, the effect on the entire system is small. Furthermore, since important data, ie, data that is difficult to reproduce, is written to both the cache memory and the external storage device at the same time, no data is lost. Therefore, highly reliable writing can be achieved.

Here, data having attributes that are easy to reproduce include temporary data such as work data. Also,
Data with attributes that are difficult to reproduce include, for example, data such as a user database.

To determine whether data is difficult to reproduce or data that is easy to reproduce, for example, the upper program car is classified, and a command immediately before a write command instructs whether the next write data belongs to one of the above attributes, and the control device If the data has an attribute that is easy to reproduce, it is stored in the cache and then written to the external storage device, and if the data has an attribute that is difficult to reproduce, it is written to the cache memory and the external storage device at the same time. Further, whether data is difficult to reproduce or data that is easy to reproduce may be determined based on the machine number of the external storage device set in advance or the storage area of the external storage device. In other words, if the write command is for a predetermined machine number or a predetermined storage area (for example, a cylinder number in a predetermined range of a magnetic disk storage device) of an external storage device, it is first written to the cache memory, then written to the external storage device, and set. If the write command is for a device other than the machine number of the external storage device or a storage area other than that of the external storage device, the data is written to both the cache memory and the external storage device at the same time.

Specifically, the control device has a path for temporarily storing data from the host device, a path for reading the data from the cache memory and writing it to an external storage device, and a path for writing the data from the host device to the cache memory. This is achieved by having a selection circuit that can freely select a path for writing to external storage in parallel.

〔Example〕

The present invention will be explained in more detail below with reference to embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.
KC). In FIG. 1, 1 is a central processing unit (CPU), 2 is a DKC, and 3 is a disk storage unit (DKU). Next, the structure within DKCZ will be explained. 201 is a microprocessor that performs the entire DKC2 and C2 operations. Further, 202 is a control memory for storing a microprogram, and 203 is a control memory for storing a microprogram.
A DKU control unit that controls the U interface, 204 a selection circuit, 205 a data transfer control unit that controls data transfer such as reading/writing between the CPUI and the DKU3, 206
207 is a selection circuit, and 207 is a flip-flop that instructs the read mode/write mode for the cache memory 209. 208 is a CPU control unit that controls the CPU interface.

The cache memory 209 has a capacity of the maximum number + MB, and is composed of a semiconductor memory.

211 is an output bus from the CPUI, and write data and commands for the DKU3 are set on this bus. 21'L is a bus from DKU3, and read data is set therein. 213 is a write data bus for the cache memory 209, and the selection circuit 20
6 selects either the output bus 211 or the read bus 212. 214 is the cache memory 20
9 is a read bus (cache bus) from 215
is the DKU bus selected by the selection circuit 204, either the cache bus 214 or the output bus 211. 22
1 is an output control signal from the microprocessor 201, and the selection circuit 206 selects the output bus 211 as the write data bus when this signal is 411 II, and selects the read bus 212 as the write data bus when it is 10''.

222 is an output control signal from the microprocessor 201, and the selection circuit 204 determines whether this signal is II I I
When it is I, the cache bus 214 is selected as the DKU bus 215, and when it is rt O71, the output bus 211 is selected as the DKU bus 215. 2
23 is a set/reset signal from the microprocessor 201 to the flip-flop 207;
is the output of the flip-flop 207, which instructs the cache memory 209 to be in read mode or “0” or write mode or “1”.

FIG. 2 is an example of a typical command sequence output from the CPUI to the DKU3. Let's briefly explain each command.

5EEK: Transfers 6 bytes and transfers the DKU head to the specified cylinder number.

Position the head number.

SET FILE MASK...Transfers a 1-byte file mask that determines the allowable range for seek and write operations.

The file mask is defined below.

(i) Bit 0.1 = OO: WRITE HA.

Disable WRITE RO bit 0.1 = 01: Disable all WRITE commands Bit 0.1 = 10: Disable all format write commands Bit 0, 1 = 11: Enable all WRITE commands (if) Bit 3.4 = OO: All 5EEKs.

(Including RECALI BRATE) Command enable bit 3.4 = 01: S'EEK CYLSEEK
Enable HH command bit 3.4 = 10: 5EEK Enable HH command bit 3.4 = 11: Disable all seek operations (iii) Bit 5 = O: DIAG WRITE
Disable command Bit 5 = 1: Allow DIAG WRITE command (i■) Bit 7 = O: Not in PCI fetch mode.

Bit 7 = 1: PCI fetch mode.

(V) Bit 2=O: Continued<WRITE:+v The data attribute of the node is easy to reproduce.

Bit 2=1=Continue<The data attribute of the WRITE command is difficult to reproduce.

(vi) Bit 6 Unused SET 5ECTOR...Sends a 1-byte sector number. An interrupt is generated when the head is positioned at the specified sector.

5EARCHID TIC...Sends a 5-byte ID byte, and if it does not match the ID read from DKU, TIC
Check the law record again by , and if it matches, TI
Proceed to process the next command in C.

WRITE DATA...Transfer write data to DKU.

Each of these commands is set on the output bus 211 and sent to the microprocessor 201. The microprocessor 201 decodes this and decodes the entire DKC2 and DKU
3. Issue a predetermined instruction to 3.

Next, the entire DKC2 and C2 will be explained. The following two methods are possible when writing data to DKU3.

(a) Write data is sent out via the output bus 211, passes through the selection circuit 206, and is temporarily stored in the cache memory 209. At this time, the microprocessor 201 controls the flip-flop 2 by the set/reset signal 223.
Set 07 to "1". When DKC2 is empty,
The microprocessor 201 resets the flip-flop 207 to "0" and sets the control signal 222 to gx 1
By setting to, the data stored in the cache memory 209 is sent to the DKU3 via the cache bus 214 and the DKU bus 215, and written to the DKU3. FIG. 3(a) is a flowchart showing the operation of (a) above.

(b) Write data is sent to the output bus 211.

By setting the control signal 221 to '1' and the control signal 222 to '0', the microprocessor 201 writes the write data on the output bus 211 to the cache memory 209 via the write data bus 213. At the same time, the write data on the output bus 211 is written to the DKU3 via the DKU bus 215. At this time, the flip-flop 207 is set to 1''. FIG. 3(b) is a flowchart showing the operation of (b) above.

SET F engineering LEMASK in the command shown in Figure 2
Depending on bit 2 of the file mask transferred (see definition (V) of the file mask above), it is possible to select whether to adopt the above (a) or (b). That is, when bit 2 is "0", the attributes of the written data can be easily reproduced, so it is okay to use the method (a) above, and when bit 2 is II I 11, the attributes of the data cannot be reproduced. Since this is difficult, method (b) above will be used. This control is performed by the microprocessor 201 that has decoded the command.

Next, do the above (a) without depending on the command from the CPUI.
The method for selecting (b) will be explained.

FIG. 4 shows a table stored in the control memory 202. The meaning of this table is to indicate the storage area in DKU3 where data with attributes that are difficult to reproduce are stored.DEV#...Device number in DKU3CC1...Cylinder number of the upper limit of the storage area CC2...
- This is the lower limit cylinder number of the storage area. A plurality of tables of this combination are stored in the control memory 202.

It may be written into the control memory 202 manually, or
A special command may be defined and written to the control memory 202 by a CPU program. When the microprogram receives the 5EEK command, it checks whether the cylinder number to be sought is registered in the table shown in FIG. If it is not registered, it is assumed that the data has attributes that are easy to reproduce, and is written to the DKU 3 using the method (a) above. If the cylinder is registered in the table in Figure 4.

Regarded as data that is difficult to reproduce, D
Write to KU3.

As described above, whether write data is written to the cache memory 201 first by specifying a command or by checking a preset storage area, and then written to the DKU3, the cache memory 209
It becomes possible to select whether to write to both DKU3 and DKU3 at the same time.

〔Effect of the invention〕

According to the present invention, data with attributes that are easy to reproduce can be written to the cache memory and then written to the DKU, and data with attributes that are difficult to reproduce can be written to both the cache memory and the DKU at the same time. It is possible to improve processing performance and configure a highly reliable disk subsystem.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of commands generated from the central processing unit shown in FIG. 1, and FIGS. 1 is a flowchart showing the operation of the embodiment shown in FIG. 1, and FIG. 4 is a diagram showing an example of a table of storage areas in the control memory shown in FIG. 1. 1...Central processing unit (CPU), 2...DKC13
... Disk storage unit (DKU), 201 ... Microprocessor, 202 ... Control memory, 204
...Selection circuit, 206...Selection circuit, 209...
cache memory. Representative Patent Attorney Tadashi Akimoto Figure 1 Figure 2 Figure 4 5EARCHID IC WRITE DATA No. 31 (a) Kimatsushe ←-DKLJ Fito vJ Outside (b) CPLJ 4DKCyn\JIL

Claims (1)

[Claims] 1. In an external storage device write control method that uses a cache memory to control an external storage device installed in a computer system, when data from a host device is written to the external storage device, data that is easy to reproduce is cached once. 1. A write control method for an external storage device, comprising writing data from a cache memory to an external storage device after storing the data in a memory, and writing data that is difficult to reproduce to both the cache memory and the external storage device at the same time.