JPH0121566Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device including a package on which an IC chip is mounted, and particularly to a terminal structure of the package that is effective in preventing electrostatic damage.

[Conventional technology]

As microfabrication technology advances, ICs are becoming more integrated and denser, and the number of electrodes that need to be connected to the outside world is also increasing significantly. As a package used to mount such an IC, for example, a flat package with a multi-pin configuration is highly economical.
It is used in a wide range of applications, from general ICs to LSIs. This is because while the standard pin spacing for general packages is 100 mils (2.54 m/m), the standard pin spacing for flat packages is 50 mils, which is half that, making high-density mounting on printed circuit boards easy.

On the other hand, the gate electrode of the IC is formed of a silicon oxide film with excellent insulating properties, and is connected to a signal terminal for external connection of the package through a signal line. Therefore, if the signal terminal comes into contact with clothing, plastic containers, or other external objects, high voltage due to static electricity generated by this will be applied to the gate electrode, which may lead to dielectric breakdown and IC failure. Become.

[The problem that the idea attempts to solve]

As ICs become more integrated and denser, and gate insulating films become thinner, their withstand voltage decreases, making IC failures due to the aforementioned dielectric breakdown more likely to occur. For example, increase the thickness of the gate insulating film to several hundred or more.
When thinned to 1000A, dielectric breakdown occurs at a low voltage of about 40 to 70V. This dielectric breakdown is different from the dielectric breakdown of a pn junction, and cannot be recovered by a single application of overvoltage. That is, the gate insulating film is destroyed and becomes conductive, causing a short circuit between the gate electrode and the substrate or source/drain electrode, resulting in malfunction of the transistor. Such a phenomenon causes a decrease in the reliability of the semiconductor device.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a semiconductor device which is effective in preventing electrostatic damage to elements connected to signal terminals using simple means.

[Means to solve the problem]

The above object is a semiconductor device comprising a package having a power supply terminal extending from a power supply potential line of a mounted IC chip and a signal terminal extending from a signal line of the IC chip. ,
This is achieved by a semiconductor device characterized in that the outermost tip exposed portion of the power supply terminal is arranged to protrude outward from the exposed portion of the signal terminal.

[Effect]

In this invention, the exposed tip of the power terminal is placed outside the exposed tip of the signal terminal, which makes it difficult for objects with static electricity to connect directly to the signal terminal. will come into contact with.

The power supply terminal is commonly connected to many terminals within the IC chip, so even if something with static electricity comes into contact with it before it contacts the signal terminal and a high voltage is applied, it will not affect the many elements connected to the power supply terminal. The applied voltage is dispersed and the element is less likely to be destroyed.

In addition, since the signal terminal is connected only to a very limited number of elements within the IC chip, if an object with static electricity comes into contact with the signal terminal first and a high voltage is applied between the signal terminal and the power supply terminal, the signal The element connected to the terminal will be destroyed, but if an object with static electricity contacts the power terminal and then the signal terminal, the potential difference between the signal terminal and the power terminal disappears, and the element connected to the signal terminal will not be destroyed. It doesn't happen.

Therefore, according to the present invention, high voltage due to static electricity can be prevented from being directly applied to the signal terminal.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a perspective view of a flat package type semiconductor device showing an embodiment of the present invention.

A flat package semiconductor device 1 on which an IC chip is mounted is provided with a plurality of protruding external connection terminals. These terminals consist of a power terminal 2 extending from the power supply potential line including the ground potential line of the IC chip and a signal terminal 3 extending from the signal line of the IC chip. It is made to protrude longer than the signal terminal 3.
This structure makes it easier for external objects to come into contact with the power supply terminal 2 before coming into contact with the signal terminal 3.

FIG. 2 is a plan view of a chip carrier package type semiconductor device showing another embodiment of the present invention, and FIG. 3 is a sectional view taken along the line AA in FIG.

Chip carrier package 4 has an IC in the center.
A chip 5 is mounted, and signal terminals 6 for external connection are provided around it. Therefore, the power supply potential lines 8 and 9 of the IC chip 5 are connected to the conductor film attached to the side surface 10 of the package 4 to serve as power supply terminals, and the signal potential line 7 of the IC chip 5 is connected to the signal terminal 6. Connecting. By arranging the power supply terminal so as to protrude outward from the signal terminal in this way, it is possible to reduce the chance of static charge being accumulated on the signal terminal, thereby helping to prevent electrostatic damage.

Note that the present invention is effective not only for the package of the above embodiment but also for semiconductor devices having package structures of other shapes.

[Effect of idea]

As explained above, according to the present invention, by arranging the exposed end of the power supply terminal of the package so that it is outside the exposed part of the signal terminal, electrostatic damage to the elements connected to the signal terminal can be significantly reduced. The reliability of the semiconductor device can be improved at low cost.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing an embodiment of the present invention, FIG. 2 is a plan view showing another embodiment of the present invention, and FIG. 3 is a sectional view taken along line AA in FIG. In the figure, 1 is a flat package type semiconductor device, 2 is a power supply terminal, 3 and 6 are signal terminals, 4 is a chip carrier package, 5 is an IC chip, 7 is a signal potential line, 8 and 9 are power supply potential lines, 10 is the side part of the chip carrier package.

Claims (1)

[Claims for Utility Model Registration] A semiconductor comprising a package having a power terminal extending from the power potential line of a mounted IC chip and a signal terminal extending from the signal line of the IC chip. What is claimed is: 1. A semiconductor device, wherein an outermost tip exposed portion of the power supply terminal is arranged to protrude outward from an exposed portion of the signal terminal.