JPH0121629B2 - - Google Patents

Info

Publication number
JPH0121629B2
JPH0121629B2 JP59129333A JP12933384A JPH0121629B2 JP H0121629 B2 JPH0121629 B2 JP H0121629B2 JP 59129333 A JP59129333 A JP 59129333A JP 12933384 A JP12933384 A JP 12933384A JP H0121629 B2 JPH0121629 B2 JP H0121629B2
Authority
JP
Japan
Prior art keywords
small electronic
printed wiring
package
electronic component
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP59129333A
Other languages
Japanese (ja)
Other versions
JPS6016447A (en
Inventor
Kanji Ootsuka
Hajime Murakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59129333A priority Critical patent/JPS6016447A/en
Publication of JPS6016447A publication Critical patent/JPS6016447A/en
Publication of JPH0121629B2 publication Critical patent/JPH0121629B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0444—Apparatus for wiring semiconductor or solid-state device
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は小型電子装置を内蔵したパツケージ
を、主として、IC、LSI用のセラミツクパツケー
ジを基板へ実装する構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure for mounting a package containing a small electronic device, mainly a ceramic package for IC or LSI, onto a substrate.

従来よりIC、LSI等の実装方式として、(1)リー
ドコネクシヨン及び(2)リードレスコネクシヨン
（半田フエースダウンコネクシヨン）等がよく知
られている。 Conventionally, (1) lead connection and (2) leadless connection (solder face down connection) are well known as mounting methods for ICs, LSIs, etc.

上記(1)は第５図ａから明らかなように、IC、
LSIパツケージの下面より横方向に延びるリード
５をプリント基板７等の配線８に半田付けするも
ので、この場合リード部分の実装密度が低下する
欠点があり、又同図ｂから明らかなように、IC、
LSIパツケージ１下面より縦方向へ折曲つて延び
るリード線５をプリント基板７等の配線上のスル
ーホール１１へ半田付けするもので、この場合、
同図ａの場合より実装密度は上るがスルーホール
のピツチＬをパツケージの幅Ｗより大きくとる必
要があり、例えば1.5mm以下とすることは困難で
ある。 As is clear from Figure 5a, (1) above indicates that IC,
The leads 5 extending laterally from the bottom surface of the LSI package are soldered to the wiring 8 of the printed circuit board 7, etc. In this case, there is a drawback that the packaging density of the lead portion is reduced, and as is clear from Figure b, I C,
A lead wire 5 extending vertically from the bottom surface of the LSI package 1 is soldered to a through hole 11 on the wiring of a printed circuit board 7, etc. In this case,
Although the packaging density is higher than in case a of the same figure, it is necessary to set the pitch L of the through holes larger than the width W of the package, and it is difficult to set it to 1.5 mm or less, for example.

上記(2)は第５図ｃを参照し、IC、LSIのパツケ
ージ主面に接続端子１２を設けておき、基板７上
の配線８に対向させて半田層９を介して直接に溶
着するものであり、この場合は実装密度は最小と
し得るが、熱的整合の関係からICパツケージと
同じ膨張率をもつ基板であることが必要である。
すなわち、パツケージがセラミツク、ガラスであ
れば、基板はそれに対応しセラミツク、ガラスを
材料とするものでなければならない。 For (2) above, referring to FIG. 5c, the connection terminal 12 is provided on the main surface of the IC or LSI package, and is welded directly to the wiring 8 on the board 7 via the solder layer 9. In this case, the packaging density can be minimized, but the substrate must have the same expansion coefficient as the IC package for thermal matching.
That is, if the package is made of ceramic or glass, the substrate must be made of ceramic or glass correspondingly.

本発明は上記問題点を解決すべくなされたもの
であり、その目的は次の通りである。 The present invention has been made to solve the above problems, and its objects are as follows.

即ち、リードレスコネクシヨンに近い実装密度
を有する小型電子部品の実装構造であつて、か
つ、小型電子部品とそれを実装するためのプリン
ト配線基板との熱的不整合の影響を受けることの
ない小型電子部品の実装構造を提供することにあ
る。 In other words, it is a mounting structure for small electronic components that has a packaging density close to that of a leadless connection, and is not affected by thermal mismatch between the small electronic components and the printed wiring board on which they are mounted. The object of the present invention is to provide a mounting structure for small electronic components.

そのための本発明の要旨は、小型電子装置を内
蔵し、かつ、二主面および側面を有するパツケー
ジ本体と前記パツケージの一主面から導出された
複数のピン状リードを有する小型電子部品と、プ
リント配線基板を有する小型電子部品の実装構造
において、前記小型電子部品の前記一主面は前記
プリント配線基板のプリント配線のある面に対向
するように配置され、前記ピン状リードの先端部
はその先端断面が前記プリント配線基板のプリン
ト配線のある前記面に略対向するように固着さ
れ、前記小型電子部品は前記ピン状リードにより
前記プリント配線基板のプリント配線のある前記
面に対して支持されていることを特徴とする小型
電子部品の実装構造にある。 The gist of the present invention for this purpose is to provide a small electronic component that includes a small electronic device and has a package body having two main surfaces and a side surface, a plurality of pin-shaped leads led out from one main surface of the package, and a printed circuit board. In the mounting structure of a small electronic component having a wiring board, the one principal surface of the small electronic component is arranged to face a surface with printed wiring of the printed wiring board, and the tip of the pin-shaped lead is located at the tip of the printed wiring board. The small electronic component is fixed so that its cross section substantially faces the surface of the printed wiring board where the printed wiring is located, and the small electronic component is supported by the pin-like lead to the surface of the printed wiring board where the printed wiring is located. It is a mounting structure for small electronic components that is characterized by the following.

なお、ここで「小型電子部品の一主面」とは、
例えば、第３図の絶縁基板７（プリント配線基
板）の配線８のある面と対向するセラミツクパツ
ケージの一の面をいう。また、「小型電子部品の
ピン状リードの先端部」とは、例えば、第３図の
ピン状リード１０が絶縁基板７の配線８に固着さ
れている部分近傍をいう。 Note that "one main surface of a small electronic component" here means
For example, it refers to one surface of a ceramic package that faces the surface on which the wiring 8 of the insulating substrate 7 (printed wiring board) in FIG. 3 is located. Further, "the tip of a pin-shaped lead of a small electronic component" refers to, for example, the vicinity of the portion where the pin-shaped lead 10 shown in FIG. 3 is fixed to the wiring 8 of the insulating substrate 7.

以下、本発明に対する比較例および本発明の実
施例につき説明する。 Comparative examples for the present invention and examples of the present invention will be described below.

比較例 第１図は本発明を成すための前提として本発明
者が考えたパツケージを示し、１はセラミツクパ
ツケージ本体、２は本体に内装されたIC、LSI半
導体素子、３は封止蓋、４はメタライズ配線層、
５はリードで配線層に銀ロウ層６を介して取付け
られ先端を内側に折り曲げてある。上記パツケー
ジにおいて、リードの配線基板への最大取付間隔
Ｌはパツケージの横幅Ｗとほぼ等しく、上記リー
ドのパツケージ取付部から基板への取付部までの
リード長さl1はリードの幅（厚さ）ｔにほぼ等し
いか又はそれより大きくとつてある。例えばＬは
Ｗと同じ1.5mmとする。又、パツケージ下面から
基板取付部までのリード長さl1＝0.25〜10とし、
このリードを取付ける銀ロウのパツケージ下面よ
りの長さl2＝0.25〜５とすると、銀ロウを取除い
たリードの有効長さｌ＝l1−l2をリード厚さｔ＝
0.25mmに対して、例えばlnio≧0.25mmとする。Comparative Example Figure 1 shows a package conceived by the inventor as a premise for accomplishing the present invention, in which 1 is a ceramic package body, 2 is an IC or LSI semiconductor element built into the body, 3 is a sealing lid, and 4 is the metallized wiring layer,
A lead 5 is attached to the wiring layer via a silver solder layer 6, and its tip is bent inward. In the above package, the maximum mounting interval L between the leads to the wiring board is approximately equal to the width W of the package, and the lead length l1 from the package mounting part to the board mounting part is the lead width (thickness). It is set to be approximately equal to or larger than t. For example, let L be the same as W, 1.5 mm. Also, the lead length l 1 from the bottom surface of the package cage to the board mounting part should be 0.25 to 10,
Assuming that the length of the silver solder to which this lead is attached from the bottom surface of the package l 2 = 0.25 to 5, the effective length of the lead after removing the silver solder l = l 1 - l 2 is the lead thickness t =
For example, l nio ≧0.25 mm for 0.25 mm.

第２図は上記パツケージ（小型電子部品）をプ
リント基板に取付けた場合の形態を示し、７は樹
脂基板、８は銅等から成るプリント配線、９は半
田である。 FIG. 2 shows the form in which the above-mentioned package (small electronic component) is attached to a printed circuit board, where 7 is a resin board, 8 is a printed wiring made of copper or the like, and 9 is solder.

実施例 第３図及び第４図ａ，ｂは本発明の実施例であ
る。Embodiment FIGS. 3 and 4 a and b show embodiments of the present invention.

第３図はグリツドアレイタイプのパツケージを
絶縁基板７に実装した例で、１０はパツケージ本
体１に埋め込まれた断面円形のピン状リードであ
る。この場合lnio＝リード径φで、通常0.45〜0.5
mmが採用される。 FIG. 3 shows an example in which a grid array type package is mounted on an insulating substrate 7, and 10 is a pin-shaped lead with a circular cross section embedded in the package body 1. In this case, l nio = lead diameter φ, usually 0.45 to 0.5
mm is adopted.

第４図ａ，ｂは第３図におけるピン状リード１
０の他の形態を示し、第４図ａは本体の内部から
ピン状リードが導出する場合、同図ｂは本体下部
からリードが導出する場合である。 Figures 4a and b are pin-shaped leads 1 in Figure 3.
FIG. 4A shows a case where the pin-shaped lead is led out from inside the main body, and FIG. 4B shows a case where the lead is led out from the bottom of the main body.

本発明によれば、リードレスコネクシヨンに近
い実装密度を有し、かつ、小型電子部品とそれを
実装するためのプリント配線基板との熱的不整合
の影響を受けることのない小型電子部品の実装構
造を得ることができる。 According to the present invention, a small electronic component has a packaging density close to that of a leadless connection and is not affected by thermal mismatch between the small electronic component and the printed wiring board on which it is mounted. A mounting structure can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明を成すための前提として本発明
者が考えたパツケージ断面図、第２図はこのパツ
ケージを配線基板に取付けた状態を示す一部断面
図、第３図は本発明の実施例の断面図、第４図
ａ，ｂは同じくその部分図である。第５図ａ〜ｃ
は従来例によるパツケージとその取付け態様を示
す正面図（一部断面図）である。 １……セラミツクパツケージ本体、２……IC、
LSI半導体素子、３……封止蓋、４……メタライ
ズ配線、５……リード、６……半田層、７……絶
縁基板、８……配線、９……半田層、１０……ピ
ン状リード、１１……スルーホール、１２……接
続端子、ｌ，lnio……リード有効長。 Fig. 1 is a sectional view of a package that the inventor considered as a premise for realizing the present invention, Fig. 2 is a partial sectional view showing the package attached to a wiring board, and Fig. 3 is an implementation of the present invention. The sectional view of the example, FIGS. 4a and 4b, is also a partial view thereof. Figure 5 a-c
1 is a front view (partially sectional view) showing a conventional package and its mounting manner; FIG. 1... Ceramic package body, 2... IC,
LSI semiconductor element, 3... Sealing lid, 4... Metallized wiring, 5... Lead, 6... Solder layer, 7... Insulating substrate, 8... Wiring, 9... Solder layer, 10... Pin shape Lead, 11...Through hole, 12...Connection terminal, l, l nio ...Lead effective length.

Claims (1)

【特許請求の範囲】 １ 小型電子装置を内蔵し、かつ、二主面および
側面を有するパツケージ本体と前記パツケージの
一主面から導出された複数のピン状リードを有す
る小型電子部品と、プリント配線基板を有する小
型電子部品の実装構造において、前記小型電子部
品の前記一主面は前記プリント配線基板のプリン
ト配線のある面に対向するように配置され、前記
ピン状リードの先端部はその先端断面が前記プリ
ント配線基板のプリント配線のある前記面に略対
向するように固着され、前記小型電子部品は前記
ピン状リードにより前記プリント配線基板のプリ
ント配線のある前記面に対して支持されているこ
とを特徴とする小型電子部品の実装構造。 ２ 前記ピン状リードの一部は前記パツケージ本
体内部に埋め込まれていることを特徴とする特許
請求の範囲第１項記載の小型電子部品の実装構
造。[Scope of Claims] 1. A small electronic component containing a small electronic device and having a package body having two main surfaces and a side surface, a plurality of pin-shaped leads led out from one main surface of the package, and printed wiring. In the mounting structure of a small electronic component having a board, the one main surface of the small electronic component is arranged to face a printed wiring surface of the printed wiring board, and the tip of the pin-shaped lead has a cross section of the tip. is fixed to the surface of the printed wiring board so as to be substantially opposite to the surface of the printed wiring board, and the small electronic component is supported by the pin-shaped lead to the surface of the printed wiring board that has the printed wiring. A mounting structure for small electronic components featuring: 2. The small electronic component mounting structure according to claim 1, wherein a part of the pin-shaped lead is embedded inside the package body.
JP59129333A 1984-06-25 1984-06-25 Miniature electronic component Granted JPS6016447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59129333A JPS6016447A (en) 1984-06-25 1984-06-25 Miniature electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59129333A JPS6016447A (en) 1984-06-25 1984-06-25 Miniature electronic component

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP7315576A Division JPS52156559A (en) 1976-06-23 1976-06-23 Small electronic device packaging package

Publications (2)

Publication Number Publication Date
JPS6016447A JPS6016447A (en) 1985-01-28
JPH0121629B2 true JPH0121629B2 (en) 1989-04-21

Family

ID=15007009

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59129333A Granted JPS6016447A (en) 1984-06-25 1984-06-25 Miniature electronic component

Country Status (1)

Country Link
JP (1) JPS6016447A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63158892A (en) * 1987-12-11 1988-07-01 株式会社日立製作所 Mounting structure of miniature electronic parts
JPH01313969A (en) * 1988-06-13 1989-12-19 Hitachi Ltd Semiconductor device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4857652U (en) * 1971-11-02 1973-07-23
JPS4888942U (en) * 1972-01-31 1973-10-26
JPS5529584B2 (en) * 1972-10-04 1980-08-05
JPS5532022B2 (en) * 1973-05-07 1980-08-22
JPS50145262U (en) * 1974-05-18 1975-12-01

Also Published As

Publication number Publication date
JPS6016447A (en) 1985-01-28

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