JPH065732A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH065732A JPH065732A JP4159286A JP15928692A JPH065732A JP H065732 A JPH065732 A JP H065732A JP 4159286 A JP4159286 A JP 4159286A JP 15928692 A JP15928692 A JP 15928692A JP H065732 A JPH065732 A JP H065732A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- substrate
- input
- type semiconductor
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】
【目的】 半導体装置の基板への実装を高密度化するこ
とができるようにするものである。
【構成】 半導体装置の樹脂モールド筐体１３の上面ま
たは下面に凹部１６を設け、この凹部１６に入出力端子
１５を設置したものである。
(57) [Abstract] [Purpose] To enable high density mounting of a semiconductor device on a substrate. [Structure] A resin mold casing 13 of a semiconductor device is provided with a recess 16 on an upper surface or a lower surface thereof, and an input / output terminal 15 is installed in the recess 16.
Description
【０００１】[0001]
【産業上の利用分野】本発明は基板上に高密度実装する
ことができる半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which can be mounted on a substrate with a high density.
【０００２】[0002]
【従来の技術】図３は従来のＤＩＰ型半導体装置を示す
斜視図であり、図４はこのＤＩＰ型半導体装置を基板上
に実装した場合の側面図である。図において、１は入出
力端子２を２方向に設置したＤＩＰ（デュアル・インラ
イン・パッケージ）型に代表される挿入形の半導体装置
である。2. Description of the Related Art FIG. 3 is a perspective view showing a conventional DIP type semiconductor device, and FIG. 4 is a side view when the DIP type semiconductor device is mounted on a substrate. In the figure, reference numeral 1 denotes an insertion type semiconductor device represented by a DIP (dual inline package) type in which input / output terminals 2 are installed in two directions.
【０００３】このＤＩＰ型半導体装置１の入出力端子２
を基板３の図示せぬスルーホールに挿入し、半田で接合
するものである。The input / output terminal 2 of this DIP type semiconductor device 1
Is inserted into a through hole (not shown) of the substrate 3 and joined by soldering.
【０００４】図５は従来のＱＦＰ型半導体装置を示す斜
視図であり、図６はこのＱＦＰ型半導体装置を基板に実
装した場合の側面図である。図において、４は入出力端
子５を４方向に設置したＱＦＰ（クワッド・フラット・
パッケージ）型に代表される表面実装型の半導体装置で
ある。FIG. 5 is a perspective view showing a conventional QFP type semiconductor device, and FIG. 6 is a side view when the QFP type semiconductor device is mounted on a substrate. In the figure, 4 is a QFP (quad flat type) in which the input / output terminals 5 are installed in 4 directions.
This is a surface-mount type semiconductor device represented by a package type.
【０００５】このＱＦＰ型半導体装置４を基板６に搭載
し、その入出力端子５を基板６の表面の電極部に半田で
接合するものである。This QFP type semiconductor device 4 is mounted on a substrate 6, and its input / output terminals 5 are joined to the electrode portions on the surface of the substrate 6 by soldering.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記構
成の半導体装置、特にＤＩＰ型半導体装置では、基板に
スルーホールを設けなければならないため、スルーホー
ルの部分には基板の配線パターンを設けることができな
い。However, in the semiconductor device having the above-mentioned structure, particularly the DIP type semiconductor device, since the through hole has to be provided in the substrate, the wiring pattern of the substrate cannot be provided in the through hole portion. .
【０００７】また、ＱＦＰ型半導体装置では、入出力端
子が同一ピッチの場合、入出力端子数を増やすと、ＱＦ
Ｐ型半導体装置の樹脂筺体の寸法が大きくなる。Further, in the QFP type semiconductor device, if the number of input / output terminals is increased when the input / output terminals have the same pitch, QF
The size of the resin housing of the P-type semiconductor device becomes large.
【０００８】このように、ＤＩＰ型半導体装置およびＱ
ＦＰ型半導体装置のいずれの入出力端子の設け方でも、
基板への高密度実装という点から満足できるものが得ら
れないという問題点があった。In this way, the DIP type semiconductor device and the Q
Regardless of how the input / output terminals of the FP type semiconductor device are provided,
There is a problem in that a satisfactory product cannot be obtained in terms of high-density mounting on a substrate.
【０００９】本発明は、以上述べた基板上への高密度実
装が満足できないという問題点を除去するため、半導体
装置の筺体の平面内に、入出力端子を設置する優れた半
導体装置を提供することを目的とする。The present invention provides an excellent semiconductor device in which input / output terminals are installed in the plane of the housing of the semiconductor device in order to eliminate the above-mentioned problem that the high-density mounting on the substrate cannot be satisfied. The purpose is to
【００１０】[0010]
【課題を解決するための手段】本発明に係る半導体装置
は、半導体装置の筺体上面または下面に凹部を設け、こ
の凹部に入出力端子を設置するものである。A semiconductor device according to the present invention is one in which a recess is provided in the upper or lower surface of a housing of the semiconductor device, and an input / output terminal is installed in this recess.
【００１１】[0011]
【作用】本発明は基板への実装を高密度に行なうことが
できる。The present invention enables high-density mounting on a substrate.
【００１２】[0012]
【実施例】図１は本発明に係る半導体装置の一実施例を
示す断面図であり、図２はこの半導体装置を基板に実装
した場合の一部破断した側面図である。図において、７
は半導体素子、８はこの半導体素子７を固着したダイパ
ット、９は一方の面に導体１０を配線し、他方の面に導
体１１を配線し、この導体１０と導体１１をスルーホー
ル１２で接続した絶縁板、１３は樹脂モールド、１４は
半導体素子７の電極と導体１０を接続する金属細線、１
５は一端が導体１１に接続し、他端が半導体装置の筺体
下面凹部１６に配置した入出力端子である。1 is a sectional view showing an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a partially cutaway side view of the semiconductor device mounted on a substrate. In the figure, 7
Is a semiconductor element, 8 is a die pad to which the semiconductor element 7 is fixed, 9 is a conductor 10 on one side and a conductor 11 is on the other side, and the conductor 10 and the conductor 11 are connected by a through hole 12. An insulating plate, 13 is a resin mold, 14 is a thin metal wire that connects the electrode of the semiconductor element 7 and the conductor 10, 1
Reference numeral 5 is an input / output terminal, one end of which is connected to the conductor 11 and the other end of which is arranged in the bottom surface recess 16 of the semiconductor device.
【００１３】この構成による半導体装置を基板３上に実
装する場合、図２に示すように、その入出力端子１５
は、筺体下面凹部１６に設けたので、接合材料１７によ
り、基板３上の配線パターン（図示せず）に接合するこ
とができる。When the semiconductor device having this structure is mounted on the substrate 3, as shown in FIG.
Since it was provided in the recess 16 on the lower surface of the housing, it can be bonded to the wiring pattern (not shown) on the substrate 3 by the bonding material 17.
【００１４】このように、半導体素子の筺体下面に設け
た凹部１６の面積全てを入出力端子として使用すること
ができ、基板への高密度実装を行なうことができる。As described above, the entire area of the recess 16 provided on the lower surface of the housing of the semiconductor element can be used as the input / output terminal, and high-density mounting on the substrate can be performed.
【００１５】なお、上述の実施例では、入出力端子を、
半導体装置の筺体の下面に設置した場合を示したが、こ
れに限定せず、筺体の上面に設けてもよいことはもちろ
んである。In the above embodiment, the input / output terminals are
Although the case where it is installed on the lower surface of the housing of the semiconductor device is shown, it is not limited to this, and it goes without saying that it may be installed on the upper surface of the housing.
【００１６】[0016]
【発明の効果】以上詳細に説明したように、本発明に係
る半導体装置によれば、入出力端子を半導体装置の筺体
の上面または下面に設置したので、基板への実装密度を
上げることができる効果がある。As described in detail above, according to the semiconductor device of the present invention, since the input / output terminals are provided on the upper surface or the lower surface of the housing of the semiconductor device, the mounting density on the substrate can be increased. effective.
【図１】本発明に係る半導体装置の一実施例を示す断面
図である。FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention.
【図２】図１の半導体装置を基板に実装した場合を示す
一部破断した側面図である。FIG. 2 is a partially cutaway side view showing a case where the semiconductor device of FIG. 1 is mounted on a substrate.
【図３】従来のＤＩＰ型半導体装置を示す斜視図であ
る。FIG. 3 is a perspective view showing a conventional DIP type semiconductor device.
【図４】図３の半導体装置を基板に実装した場合を示す
側面図である。FIG. 4 is a side view showing a case where the semiconductor device of FIG. 3 is mounted on a substrate.
【図５】従来のＱＦＰ型半導体装置を示す斜視図であ
る。FIG. 5 is a perspective view showing a conventional QFP type semiconductor device.
【図６】図５の半導体装置を基板に実装した場合を示す
側面図である。6 is a side view showing a case where the semiconductor device of FIG. 5 is mounted on a substrate.
７ 半導体素子 ８ ダイパット ９ 絶縁板 １０，１１ 導体 １２ スルーホール １３ 樹脂モールド １５ 入出力端子 7 semiconductor element 8 die pad 9 insulating plate 10, 11 conductor 12 through hole 13 resin mold 15 input / output terminal
Claims (1)
を設け、この凹部に入出力端子を設置したことを特徴と
する半導体装置。1. A semiconductor device, wherein a recess is provided on an upper surface or a lower surface of a housing of the semiconductor device, and an input / output terminal is installed in the recess.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04159286A JP3107648B2 (en) | 1992-06-18 | 1992-06-18 | Semiconductor device |
| JP2000129910A JP3589941B2 (en) | 1992-06-18 | 2000-04-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04159286A JP3107648B2 (en) | 1992-06-18 | 1992-06-18 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000129910A Division JP3589941B2 (en) | 1992-06-18 | 2000-04-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH065732A true JPH065732A (en) | 1994-01-14 |
| JP3107648B2 JP3107648B2 (en) | 2000-11-13 |
Family
ID=15690482
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04159286A Expired - Fee Related JP3107648B2 (en) | 1992-06-18 | 1992-06-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3107648B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102414635A (en) * | 2009-04-28 | 2012-04-11 | 三菱电机株式会社 | instruction generator |
| JP2023084224A (en) * | 2021-12-07 | 2023-06-19 | 三菱電機株式会社 | semiconductor equipment |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1992020097A1 (en) | 1991-04-26 | 1992-11-12 | Citizen Watch Co., Ltd. | Semiconductor device and manufacturing method therefor |
-
1992
- 1992-06-18 JP JP04159286A patent/JP3107648B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102414635A (en) * | 2009-04-28 | 2012-04-11 | 三菱电机株式会社 | instruction generator |
| US8897901B2 (en) | 2009-04-28 | 2014-11-25 | Mitsubishi Electric Corporation | Command generator |
| JP2023084224A (en) * | 2021-12-07 | 2023-06-19 | 三菱電機株式会社 | semiconductor equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3107648B2 (en) | 2000-11-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5057805A (en) | Microwave semiconductor device | |
| US8089141B1 (en) | Semiconductor package having leadframe with exposed anchor pads | |
| EP0521335B1 (en) | Semiconductor device mounted on a substrate | |
| US7176062B1 (en) | Lead-frame method and assembly for interconnecting circuits within a circuit module | |
| KR970013236A (en) | Chip Scale Package with Metal Circuit Board | |
| US4949220A (en) | Hybrid IC with heat sink | |
| JPH05109802A (en) | Semiconductor device | |
| US5949651A (en) | Quad flat pack integrated circuit package | |
| US5446317A (en) | Single in-line package for surface mounting | |
| US5861669A (en) | Semiconductor package for surface mounting | |
| JP2902918B2 (en) | Surface mount type semiconductor device | |
| JPH065732A (en) | Semiconductor device | |
| JP2798108B2 (en) | Hybrid integrated circuit device | |
| JP2524482B2 (en) | QFP structure semiconductor device | |
| JP2538407B2 (en) | Surface mount semiconductor device | |
| JP2000323625A (en) | Semiconductor device | |
| JP3524360B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH0214558A (en) | Semiconductor integrated circuit device | |
| JP2913500B2 (en) | Semiconductor device | |
| JPH01270256A (en) | Semiconductor device | |
| JPH0121629B2 (en) | ||
| KR930017152A (en) | Semiconductor package | |
| JPH0685102A (en) | Semiconductor integrated circuit device | |
| JPH0576052U (en) | Multi-terminal IC package | |
| JPH03284866A (en) | Lead frame |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20000822 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070908 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080908 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080908 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090908 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090908 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100908 Year of fee payment: 10 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100908 Year of fee payment: 10 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100908 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110908 Year of fee payment: 11 |
|
| LAPS | Cancellation because of no payment of annual fees |