JPH01217664A - Fault detecting system for multiprocessor system - Google Patents

Abstract

PURPOSE:To detect the faults of plural processors via a single fault monitor timer device by securing such constitution where an interruption produced from the fault monitor timer device owing to the fault of a certain processor is accepted and the faulty processor is discriminated through a memory area for a processor transmitting a health signal. CONSTITUTION:At the output time point of a health signal, a health signal output selection means 60 selects the processors 1-N which transmit the system time points obtained from a system time area and the health signals received from a health signal output processor memory area 50. In case an interruption is received from a fault monitor timer device 10 when either one of the processors 1-N produces the abnormality, a faulty processor discriminating means 90 detects the faulty processor. Thus a single device 10 can detect the faults of plural processors 1-N.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a fault detection method for a multiprocessor system, and more particularly to a fault detection method for a processor.

[Conventional technology]

In conventional fault detection methods in multiprocessor systems, fault monitoring timer devices are provided as external devices for the number of processors, and each processor and fault monitoring timer device are in one-to-one correspondence. Anomaly detection is done by outputting a signal to the timer device at regular intervals as a health signal indicating that the processor is normal, and when the health signal is interrupted, the fault monitoring timer device generates an interrupt as a processor error. I was going.

[Problem to be solved by the invention]

In the conventional fault detection method described above, fault monitoring timer devices are required for each processor.

Since each processor outputs a health signal, the overhead of fault detection processing for the entire system is large, and furthermore, when the fault monitoring timer device detects an abnormality, an interrupt is generated for the faulty processor. There is a drawback that interrupt processing from the fault monitoring timer device is not always performed normally.

[Means to solve the problem]

According to the present invention, a main memory, a plurality of processors connected to the main memory via a bus, and a plurality of processors that operate independently of the processor, and when a health signal is not received from the processor within a certain period of time, a health signal is sent at the end. A multiprocessor system is provided with a fault monitoring timer device that generates an interrupt to a processor that outputs a signal, and an external timer device that operates independently of the processor and measures time.

The main memory includes a system time area updated by the external timer device.

and a health signal output processor storage area for storing a processor that outputs a health signal to the failure monitoring timer device.

Each of the processors includes a health signal output selection unit that reads time from the system time area and selects which processor will output a health signal to the fault monitoring timer device, and health signal output means for outputting a health signal, a fault monitoring timer device for accepting an interrupt when the fault monitoring timer device generates an interrupt due to a fault in one of the processors; and a means for accepting an interrupt from the health signal output processor storage area. A multiprocessor system failure detection method is obtained, which is characterized by having a failure processor determination means for determining a processor in which a failure has occurred.

[Effect]

At the time of outputting the health signal, the health signal output selection means selects the system time obtained from the system time area and the processor that outputs the health signal from the health signal output processor storage area.

At the time of an interrupt from the fault monitoring timer device when an abnormality occurs in any of the processors, the faulty processor determining means detects the faulty processor, and the single fault monitoring timer device detects the faulty processor. failures can be detected.

〔Example〕

Next, two aspects of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment in which there are N processors, including processors 1 to N, a fault monitoring timer device 10°, an external timer device 20. and a main memory 3o.

The main memory 30 includes a system time area 4o that stores the time measured by the external timer device 20.

It has a health signal output processor storage area 50 that stores processors that output health signals to the fault monitoring timer device 10. Each processor.

Health signal output selection means 60 for selecting which of the processors 1 to N will output a health signal from the system time area 40 and the health signal output processor storage area 50. A health signal output means 70 for outputting a health signal to the fault monitoring timer device 10; a fault monitoring timer device interrupt that accepts an interrupt when the fault monitoring timer device 10 generates an interrupt in the event of a fault in any of the processors 1 to N; Reception is by means 80. and health signal output processor storage area 5
It has a faulty processor determining means 9o for determining a processor in which a fault has occurred from zero. Note that these means 60, 70, 80 . and 9o.

It is shown as being stored as a program in the main memory 30.

If the fault monitoring timer device 10 does not receive a health signal for a certain period of time, it will cause an interrupt to the processor that last outputted the health signal, and this certain period of time is defined as a monitoring time T. If the time interval at which each processor 1 to N outputs a health signal to the fault monitoring timer device 10 is the health signal output time interval t, then t<T<2t between the two. ...There is the relationship (1).

FIG. 2 is a diagram chronologically showing the operation of outputting a health signal to the fault monitoring timer device 10 when all the processors 1 to N are normal.

First, with reference to FIG. 2, the operation of the present invention when all processors are normal will be explained in chronological order.

The operation when processor n outputs a health signal at system time Tn will be described in detail with reference to FIGS. 2 and 4.

In processor n, the health signal output selection means 60 selects the health signal output at system time Tn.

Referring to FIG. 4, in this selection, first, time Tn is read out from the system' time area 40 and determined to be the health signal output timing (step 61).

Next, the processor n-1 that last outputted the health signal is read from the health signal output processor storage area 50 (step 62). Therefore, the processor n = ((n-1)+1) that will output the health signal next is selected (
Step 63). Finally, the health signal output processor storage area 50 is updated to the selected processor n (step 64). The selected processor n outputs a health signal to the fault monitoring timer device 10 by the health signal output means 70.

Next, after a lapse of time, that is, at time Tn+1, the health signal output selection means 60 again selects the processor n+1 as the health signal output processor.

n+1 is stored in the health signal output processor storage area 50, and the health signal output means 70 outputs the processor n.
+1, a health signal is output to the fault monitoring timer device 10.

As described above, when all processors 1 to N are normal, processors 2 and 3 are loaded in order from 7° processor 1.
. . . N and a health signal are output at a health signal output time interval t.

FIG. 3 is a chronological diagram showing the operation when processor n+1 becomes a failure.

The fault detection operation when processor n+1 becomes faulty at system time Tn' will be described in detail with reference to FIGS. 3 and 5.

At system time Tn, the health signal output selection means 6
0 selects the processor n, the health signal output processor storage area 50 is updated with the processor n, and the health signal output means 70 outputs a health signal to the fault monitoring timer device 10.

Next, at system time Tn', processor n + 1
Suppose that a problem occurs. Here, system time Tn+1
Processor n + 1 should be selected as the health signal output processor in
is in trouble, so no health signal is output.

Therefore, at system time Tn+1, the fault monitoring timer device 10 causes an interrupt to the processor n that last outputted the health signal. The processor n accepts the fault monitoring timer device interrupt by the means 80, and receives the fault monitoring timer device 1.
Accepts interrupts from 0. Finally, the faulty processor determining means 90 identifies the processor in which the fault has occurred.

Referring to FIG. 5, in this determination, first, the processor n that last outputted the health signal is read out from the health signal output processor storage area 50 (Stella 7'91),
The processor in which the failure has occurred is determined to be processor n + 1 (step 92).

Through the steps described above, a processor in which a failure has occurred is detected.

〔Effect of the invention〕

As described above, the present invention has the advantage that a single fault monitoring timer device can detect a fault in each processor without having to provide fault monitoring timer devices corresponding to the number of processors.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of an embodiment of the present invention, Fig. 2 is a time chart showing the health signal output operation in chronological order when all processors are normal, and Fig. 3 is a time chart showing the health signal output operation when all processors are normal. A time chart showing the failure detection operation in chronological order when a failure occurs. FIG. 4 is a flowchart for explaining the operation of the health signal output selection means 60 in FIG. 1, and FIG. 5 is a flowchart for explaining the operation of the faulty processor determining means 90 in FIG. 1. 1 to N... Processor, 10... Fault monitoring timer device, 20... External timer device, 30... Main memory, 4
0...System time area, 50...Health signal output processor storage area, 60...Health signal output selection means. 70... Health signal output means, 80... Fault monitoring timer device interrupt reception means, 90... Fault processor (Figure 1, Figure 2, Figure 3, Figure 4, Figure 5)

Claims (1)

[Scope of Claims] 1. A main memory, a plurality of processors connected to the main memory via a bus, and a processor that operates independently of the processors and, when a health signal is not received from the processors within a certain period of time, In a multiprocessor system comprising a fault monitoring timer device that generates an interrupt to a processor that outputs a health signal, and an external timer device that operates independently of the processor and measures time, the main memory includes the a system time area that is updated by an external timer device; and a health signal output processor storage area that stores processors that output health signals to the fault monitoring timer device; Health signal output selection means for reading time and selecting which processor outputs a health signal to the fault monitoring timer device; and health signal output means for outputting a health signal to the fault monitoring timer device. fault monitoring timer device interrupt accepting means for accepting an interrupt when the fault monitoring timer device generates an interrupt due to a fault in the processor; and faulty processor determining means for determining the faulty processor from the health signal output processor storage area. A multiprocessor system failure detection method characterized by having the following.