JPH0247947A - Common bus fault processor detection system - Google Patents

Abstract

PURPOSE:To detect a processor without disconnecting it from a common bus by counting number of times of reply and retransmission request returned within a prescribed time by each processor and discriminating a preceding processor to a processor returning the highest number of the retransmission request as a common bus fault processor. CONSTITUTION:Plural processors 2, 3 and a maintenance operation processor 4 are connected to one set of common bus of a packet exchange system and a faulty processor having a fault in the common bus 1 is supposed to be the processor 3. The processor 4 sends a state monitor support signal 21 simultaneously and the processor 1 receiving the signal 21 returns the state monitor command reply signal 22 to the processor 4 and sends a multiple address signal 23. The processor 4 receives the signal 22 to count number of times of the reply signal from the processor 1 in a reply reception signal management table 100, the processor 2 receiving the signal 23 sends a retransmission request signal 24 from the processor 3 to the processor 4 and the signal 24 is counted by a retransmission request reception signal management table 200.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a common bus failure processor detection method for detecting a failure location of a common bus in a packet switching system having a multi-processor configuration connected by a common bus.

[Conventional technology]

Conventionally, in order to detect a common bus failure processor, one of the multiple processors that perform packet switching control is automatically or manually disconnected from the common bus, and in this state, the maintenance and operation processor connected to the common bus is disconnected from the other operating processors. By sending diagnostic information to each of the middle processors and diagnosing whether each processor receives the diagnostic information correctly, it is possible to diagnose whether the processor disconnected from the common bus is normal or not, and if it is normal, the next processor is A faulty processor on the common bus was detected by sequentially disconnecting the processors from the common bus and diagnosing them.

[Problem to be solved by the invention]

The conventional common bus failure processor detection method described above searches multiple processors that perform packet switching control one by one, so it has the disadvantage that it takes too much time to search when there are many processors configuring a packet switching system. There is. Furthermore, since the search is performed without disconnecting the processor from the common bus, it has the disadvantage that it cannot be applied to a running system.

[Means to solve the problem]

The common bus failure processor detection method of the present invention includes a plurality of first processors that perform packet switching control, a second processor that performs maintenance and operation for the first processors, and a plurality of processors that perform maintenance operations on the first processors and the second processors. a common bus connecting the processors, the second processor transmits a status monitoring instruction signal to the first processor in a broadcast format at regular intervals, and the number of times the status monitoring response signal and retransmission request signal are received; is provided with a function of writing the status monitoring instruction signal into a received signal management table, and each of the first processors returns the status monitoring response signal when it receives the status monitoring instruction signal within a certain period of time, and returns the status monitoring response signal when it does not receive the status monitoring instruction signal. A function of returning the retransmission request signal is provided, and the second processor checks the tendency of retransmission on the common bus based on the number of times the first processor sends out the retransmission request signal more than a certain number of times within a certain period of time. This configuration detects failure points on the common bus.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of a multiprocessor-configured packet switching system to which the present invention is applied.

This packet switching system is comprised of a set of common buses 1, a plurality of processors 2 and 3 connected to the common bus 1 that perform packet switching, and a maintenance and operation processor 4. Here, it is assumed that among the processors 2 and 3, an abnormal processor having a failure in the common bus 1 is referred to as processor 3.

The operation will be explained with reference to FIGS. 2 and 3. The maintenance operation processor sends out the condition monitoring instruction signal 21 by broadcast (step 11), and the processor (1) that received the condition monitoring instruction signal 21 returns the condition monitoring response signal 22 to the maintenance operation processor (step 12). A notification signal 23 is sent out (step 13). When the maintenance operation processor receives the status monitoring response signal 22 from the processor (1), it counts up the number of times the response has been received from the processor (1) in the response reception signal management table 100 (step 14).
). The processor (2) that receives the broadcast signal 23 causes a common bus failure and is unable to send out a response and broadcast signal (step 15). Since the processor (3) does not receive the status monitoring instruction signal within tsec, it sends a retransmission request signal 24 to the maintenance and operation processor (step 16). The maintenance operation processor that receives the retransmission request signal 24 counts up the number of times the retransmission request is received from the processor (3) in the retransmission request reception signal management table 200 (step 17).
. The maintenance and operation processor performs these processes at intervals of Tsec, and after a certain period of time, the received signal management table 100,
200 and determines that there is a failure in the common bus of the processor immediately preceding the processor with a large number of retransmission request signal output ports.

〔Effect of the invention〕

As explained above, according to the present invention, each processor counts the number of responses and retransmission requests returned within a certain period of time in response to the broadcast status monitoring instruction signal periodically sent by the maintenance and operation processor, and By determining that the processor immediately before the processor that has returned a large number of request signals is the common bus failure processor being searched for, it is possible to detect the processor without disconnecting it from the common bus. It can also be applied to systems in operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the flow of information in the embodiment, and FIG. 3 is a diagram showing a received signal management table in the embodiment. 1... Common bus, 2, 3... Processor, 4 Maintenance and operation processor, 100, 200... Received signal management table. Kaya Kaya

Claims (1)

[Claims] a plurality of first processors that perform packet switching control;
a second processor that performs maintenance and operation on the first processor; and a common bus that connects the first processor and the second processor; A function is provided for sending out a status monitoring instruction signal in a broadcast format at regular intervals and writing the number of times a status monitoring response signal and a retransmission request signal have been received into a received signal management table, and each of the first processors is provided with a function of returning the condition monitoring response signal when receiving the condition monitoring instruction signal and returning the retransmission request signal when not receiving the condition monitoring instruction signal,
The second processor detects a failure point on the common bus by checking the tendency of retransmission on the common bus based on the number of times the first processor sends out the retransmission request signal for a predetermined number of times or more within a predetermined time. Common bus failure processor detection method featuring features.