JPH01218093A - Thick film multilayer circuit board - Google Patents

Thick film multilayer circuit board

Info

Publication number
JPH01218093A
JPH01218093A JP63043493A JP4349388A JPH01218093A JP H01218093 A JPH01218093 A JP H01218093A JP 63043493 A JP63043493 A JP 63043493A JP 4349388 A JP4349388 A JP 4349388A JP H01218093 A JPH01218093 A JP H01218093A
Authority
JP
Japan
Prior art keywords
conductor
multilayer circuit
component
thick film
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63043493A
Other languages
Japanese (ja)
Inventor
Junko Umeda
梅田 淳子
Hiromi Isomae
磯前 博巳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP63043493A priority Critical patent/JPH01218093A/en
Publication of JPH01218093A publication Critical patent/JPH01218093A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To avoid rising of chip components by causing a surface on which the chip components are connected with their conductors to be higher than a multilayer circuit having either a region interposed between the connecting terminals of the chip components or an insulator. CONSTITUTION:A first conductor 2 and an insulator 3, 3' are printed and baked on an insulating board 1 and a conductor 2, respectively. A second conductor 4 is printed and baked so that it is connected to the conductor 2 through a via hole 7. A soldering paste is printed on a thick film multilayer board and is reflow-soldered by heating after a chip 6 has been mounted. The surface of the second conductor 4 to be soldered, i.e., the bottom surface of terminal electrodes 6a, 6b, protrudes compared to the surface of the insulator 3, so that contact between the bottom 6c of a component 6 and the top surface of an insulating section 3' can be avoided. Accordingly, it is possible to avoid rising of the component 6 due to contact of the bottom 6c of the component 6 with the insulating section 3' which is present between the electrodes of the component 6.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、厚膜多層回路基板に係り、特に面付は十[1
1接続に好適な厚膜多層回路基板に関する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a thick film multilayer circuit board, and in particular, the surface mounting is
The present invention relates to a thick film multilayer circuit board suitable for one connection.

(従来の技術) 従来の厚膜多層回路基板の一例を、第3図に示す。図に
おいて、1はセラミック基板、2は該セラミック基板1
上に形成された第1導体、3および3゜は該第1導体上
に形成された絶縁体、5は半田、6は該半田5によって
第1導体2上に円管されるチップ部品である。
(Prior Art) An example of a conventional thick film multilayer circuit board is shown in FIG. In the figure, 1 is a ceramic substrate, 2 is the ceramic substrate 1
A first conductor is formed on the first conductor, 3 and 3° are insulators formed on the first conductor, 5 is solder, and 6 is a chip component that is circularly piped onto the first conductor 2 by the solder 5. .

上記のような構成の従来のjv膜多層回路基板において
は、導電体のクロスオーバ部の絶縁及び断線防止、ある
いは半田付は部品の半田量による接続の信頼性の向上を
図ること等には留意されてきた。
In the conventional JV film multilayer circuit board with the above configuration, care must be taken to insulate the crossover portion of the conductor and prevent disconnection, or when soldering, to improve the reliability of the connection by changing the amount of solder on the parts. It has been.

前記従来技術に関連する公知の公報として、特公昭5 
7−5 6 7 9 7号公報、特開昭60−3409
6号公報、特開昭62−86792号公報などが挙げら
れる。
As a publicly known publication related to the above-mentioned prior art, Japanese Patent Publication No. 5
Publication No. 7-5 6 7 9 7, JP 60-3409
6, JP-A No. 62-86792, and the like.

(発明が解決しようとする課題) 上記従来技術は、’F.III付は接続部品、例えばチ
ップ部品6用の端子電極5a,5b下部の積層数と、該
端子電極に挟まれる領域内の、絶縁部の積層数について
配慮がされていなかった。このため、第3図のように、
端子電極6a,6bのド部の積層数が、該端子に挟まれ
る領域の積層数より少ない場合には、半田接続時に、チ
ップ部品6の底部6Cが、該領域内の絶縁部3゛に接触
し、該チップ部品6の水平が保たれなくなり傾いて、部
品の起き上り現象(ツームストン現象あるいはマンハッ
タン現象と呼ばれる)を引きおこして、接続不良を発生
する問題があった。
(Problems to be Solved by the Invention) The above-mentioned prior art is based on 'F. No consideration was given to the number of laminated layers under the terminal electrodes 5a, 5b for the connecting parts, such as the chip parts 6, and the number of laminated insulating parts in the area sandwiched between the terminal electrodes. Therefore, as shown in Figure 3,
If the number of laminated layers in the do portions of the terminal electrodes 6a, 6b is smaller than the number of laminated layers in the area sandwiched between the terminals, the bottom 6C of the chip component 6 will come into contact with the insulating part 3' in the area during solder connection. However, there is a problem in that the chip component 6 is no longer kept horizontal and is tilted, causing a phenomenon in which the component rises (referred to as a tombstone phenomenon or Manhattan phenomenon), resulting in poor connection.

本発明の目的は、前記従来技術の問題点を除去し、部品
の水平が保たれなくなることから引きおこされる、部品
の起き上り現象による接続不良を減少させ、信頼性の向
上を図ることにある。
An object of the present invention is to eliminate the problems of the prior art described above, reduce connection failures due to the rising phenomenon of parts caused by parts not being kept horizontal, and improve reliability. .

(課題を解決するための手段) 上記目的は、前記目的を達成するために、厚膜多層基板
における、半11目;1け接続部品用端子電極の下部構
造の積層数を、該端子電極に挟まれる領域内の多層回路
と同−層数、あるいは同一層数よりも多くし、前記半田
付は接続部品の底面を前記端子電極に挟まれた領域内の
多層回路より高くした点に特徴がある。
(Means for Solving the Problem) In order to achieve the above object, the number of laminated layers of the lower structure of the terminal electrode for a half-eleventh; The soldering is characterized in that the number of layers is the same as or greater than the number of layers of the multilayer circuit in the area sandwiched, and the bottom surface of the soldering component is higher than the multilayer circuit in the area sandwiched by the terminal electrodes. be.

(作用) 本発明では、半田付は接続部品用端子電極の下部構造の
積層数を、該端子電極に挟まれるd1域内の多層回路と
同一層数以上にされているので、半田付は接続部品の底
部と、絶縁部上部との接触が回避でき、それによって、
該当部品は、接続面に対して、水平が保たれるので、部
品の起き上がり現象を発生することがなくなり、接続不
良が避けられる。
(Function) In the present invention, the number of laminated layers of the lower structure of the terminal electrode for the connecting component is equal to or more than the same number of layers as the multilayer circuit in the d1 area sandwiched between the terminal electrodes, so the soldering is performed on the connecting component. Contact between the bottom of the insulator and the top of the insulator can be avoided, thereby
Since the relevant component is kept horizontal with respect to the connection surface, the phenomenon of the component lifting up does not occur, and connection failures can be avoided.

(実施例) 以下に、本発明の一実施例を、第1図により説明する。(Example) An embodiment of the present invention will be described below with reference to FIG.

第1図は、本発明による厚膜多層回路基板の要部断面図
である。図において、4は前記第1導体2に電気的に接
続された第2導体、7は第1導体2上のピアホールを示
し、これら以外の符号は第3図と同−又は同等物を示す
FIG. 1 is a sectional view of essential parts of a thick film multilayer circuit board according to the present invention. In the figure, 4 indicates a second conductor electrically connected to the first conductor 2, 7 indicates a pier hole on the first conductor 2, and other symbols are the same as or equivalent to those in FIG. 3.

本実施例は、セラミック等の絶縁基板1上に、第1導体
2を印刷焼成して形成し、ピアホール7を有する絶縁体
3,3°を、第1導体2の上に印刷焼成し、さらに第2
導体4を、ピアホール7を介して、第1導体2と接続す
るように印刷焼成して形成するものである。
In this example, a first conductor 2 is printed and fired on an insulating substrate 1 made of ceramic or the like, an insulator 3,3° having a pier hole 7 is printed and fired on the first conductor 2, and then Second
The conductor 4 is formed by printing and firing so as to be connected to the first conductor 2 through the peer hole 7.

このようにして形成した厚膜多層基板に、半田ペースト
を印刷し、チップ部品6を搭載後、加熱リフローするこ
とにより、半田5によってチップ部品6は第2導体4お
よび第1導体2に接続される。半田接続される第2導体
4の接続面、すなわち端子電極6a、5bの下部の面は
、絶縁体3”の表面よりも突出しているので、チップ部
品6の底部6cと、絶縁部3°の上面との接触が避けら
れ、チップ部品6の水平を保つことができる。このため
、チップ部品6の底部6cがチップ部品6の電極間に存
在する絶縁部3°に接触して、チップ部品6が起き上る
という現象を回避できる効果がある。
After printing a solder paste on the thus formed thick film multilayer board and mounting the chip component 6 thereon, the chip component 6 is connected to the second conductor 4 and the first conductor 2 by the solder 5 by heating and reflowing it. Ru. The connection surface of the second conductor 4 to be soldered, that is, the lower surface of the terminal electrodes 6a, 5b, protrudes from the surface of the insulator 3'', so that the bottom 6c of the chip component 6 and the insulating portion 3° are in contact with each other. Contact with the top surface is avoided, and the level of the chip component 6 can be maintained. Therefore, the bottom part 6c of the chip component 6 comes into contact with the insulating part 3° existing between the electrodes of the chip component 6, and the chip component 6 This has the effect of avoiding the phenomenon of rising.

次に、本発明の他の実施例を、第2図を参照して説明す
る。図中の符号は、前記第1図と同一物または同等物を
示す。
Next, another embodiment of the present invention will be described with reference to FIG. The reference numerals in the figures indicate the same or equivalent parts as in FIG. 1 above.

本実施例が前記第1実施例と異なる所は、前記第1実施
例においては、第1導体2と第2導体4とを接続するの
にピアホール7を使用しているが、本実施例では該ピア
ホールを用いずに接続した点である。
The difference between this embodiment and the first embodiment is that in the first embodiment, a pier hole 7 is used to connect the first conductor 2 and the second conductor 4, but in this embodiment, a pier hole 7 is used to connect the first conductor 2 and the second conductor 4. This is a point where the connection is made without using the peer hole.

本第2実施例においても、前記第1実施例と同じ効果を
得ることができることは明かである。
It is clear that the same effects as in the first embodiment can be obtained in the second embodiment as well.

(発明の効果) 本発明によれば、チップ部品の導体との接続面を、該チ
ップ部品の接続端子で挟まれた領域の多層回路あるいは
絶縁体より高くすることができるので、チップ部品の底
部が絶縁体と接触することにより引ぎおこされる、部品
の起き上がり現象を回避することができる効果がある。
(Effects of the Invention) According to the present invention, since the connection surface of the chip component with the conductor can be made higher than the multilayer circuit or insulator in the area sandwiched between the connection terminals of the chip component, the bottom of the chip component This has the effect of avoiding the rising phenomenon of parts caused by contact with insulators.

また、これにより、厚膜多層回路基板にチップ部品を搭
載接続する際の、信頼性が向上し、不良修正に要する工
数が軽減できる効果がある。
Moreover, this has the effect of improving reliability when mounting and connecting chip components on a thick film multilayer circuit board, and reducing the number of steps required to correct defects.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の要部断面図、第2図は本発
明の他の実施例の要部断面図、第3図は従来装置の断面
図である。
FIG. 1 is a sectional view of a main part of one embodiment of the present invention, FIG. 2 is a sectional view of a main part of another embodiment of the invention, and FIG. 3 is a sectional view of a conventional device.

Claims (2)

【特許請求の範囲】[Claims] (1)セラミック基板上に、電極層と絶縁層とを交互に
それぞれ一層以上印刷して積層形成してなる厚膜多層回
路基板において、半田付け接続する部品の各端子電極の
下部に位置する多層回路の構造を、該各々の端子電極に
挟まれた領域の多層回路の層数以上にしたことを特徴と
する厚膜多層回路基板。
(1) In a thick film multilayer circuit board formed by laminating one or more electrode layers and insulating layers alternately printed on a ceramic substrate, the multilayer is located below each terminal electrode of a component to be connected by soldering. 1. A thick film multilayer circuit board characterized in that the circuit structure is greater than the number of layers of the multilayer circuit in the region sandwiched between the respective terminal electrodes.
(2)前記各々の端子電極に挟まれた領域が絶縁部であ
ることを特徴とする前記特許請求の範囲第1項記載の厚
膜多層回路基板。
(2) The thick film multilayer circuit board according to claim 1, wherein the region sandwiched between the respective terminal electrodes is an insulating portion.
JP63043493A 1988-02-26 1988-02-26 Thick film multilayer circuit board Pending JPH01218093A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63043493A JPH01218093A (en) 1988-02-26 1988-02-26 Thick film multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63043493A JPH01218093A (en) 1988-02-26 1988-02-26 Thick film multilayer circuit board

Publications (1)

Publication Number Publication Date
JPH01218093A true JPH01218093A (en) 1989-08-31

Family

ID=12665240

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63043493A Pending JPH01218093A (en) 1988-02-26 1988-02-26 Thick film multilayer circuit board

Country Status (1)

Country Link
JP (1) JPH01218093A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002158429A (en) * 2000-11-16 2002-05-31 Murata Mfg Co Ltd Structure for mounting component

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002158429A (en) * 2000-11-16 2002-05-31 Murata Mfg Co Ltd Structure for mounting component

Similar Documents

Publication Publication Date Title
US10153079B2 (en) Laminated coil component and method of manufacturing the same
US7420795B2 (en) Multilayer capacitor
JP2000165007A (en) Printed circuit board, electronic component and its mounting method
US4697204A (en) Leadless chip carrier and process for fabrication of same
US6856234B2 (en) Chip resistor
JPH01218093A (en) Thick film multilayer circuit board
JPH0818285A (en) Mounting device for surface mount component and mounting method thereof
JP2000261109A (en) Wiring board
JPS63141388A (en) Manufacture of thick film circuit board
JP2020088183A (en) Wiring board and electronic device
US11943867B2 (en) Electronic component
JP4461641B2 (en) Multilayer chip thermistor and manufacturing method thereof
US7277006B2 (en) Chip resistor
JPH01171296A (en) Connecting method for printed multilayer circuit board
JPH05183250A (en) Thick film circuit board and thick film circuit board device
JPH0590435A (en) Hybrid integrated circuit
JPH0870063A (en) Hybrid integrated circuit and circuit device including the same
JP2001284757A (en) High current printed wiring board
JP2005285994A (en) Surface mount type multiple capacitors
JPH06204001A (en) Constant laminated chip resistor
JP2005285993A (en) Surface mount type multiple capacitors
JP2006173337A (en) Electronic module structure
JPH09199301A (en) Multiple chip resistors and mounting board for mounting them
JP2008205064A (en) Electronic component mounting structure
JPH02222192A (en) Wiring pattern for printed board