JPH01220016A - Bus sending circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a communication device having a bus configuration, and in particular, to transmitting a transmission signal on a data bus during a significant period of a transmission instruction control signal generated based on an address signal. This relates to a bus sending circuit that sends data to a bus.

[Prior Art] FIG. 9 shows, for example, this type of conventional bus transmission described in "Design of Interface Circuit" by Kunio Ikai (Published by CQ Publishing Co., Ltd. on December 20, 1980, page 37). FIG. 2 is a diagram showing the circuit modified to make it easier to understand.

In the same figure, (la) to (1d) are bus sending circuit boards having the above-mentioned bus sending outlet paths, (2) is a data bus commonly connected to each bus sending circuit, and (3) is this data bus.
(4) is an address bus commonly connected to each bus sending circuit; (5) is a pull-up resistor that brings this address bus to "H"level; (6)
A unique card address is set internally, and a parallel address signal ADR is transmitted on the address bus (4).
When S and the card address match, an address-several output circuit outputs an address match signal AE, (7) inputs the address match signal AF- and outputs a sending instruction control C0 that makes "L" level significant. The gate (8) has an output enable terminal τ lower, and by adding the sending instruction control signal C0 to this, the data S is output only during its significant period.
D0 is inverted and sent as the sending signal SD to the data bus (2)
This is a 3-state bus driver gate that sends signals upward.

Next, the operation will be explained with reference to FIG. 5 as well. For example, if the card address of the bus sending circuit board (1a) is "
For example, the 2-bit address signal A transmitted via the address bus (4)
DRS (lower bit is ADR5a, upper bit is AD
It is assumed that RSb) is also "1". Bus sending circuit board (
The address-number circuit (6) of 1a) sends out an address match signal AE of "H" level. This address match signal A
E is inverted by the gate (7) and becomes the sending instruction control signal C.
0 to the output enable terminal OE of the bus driver gate (8). As a result, while the sending support control signal C0 is at the significant °L'' level, the output data SDO is inverted by the bus driver gate (8) and sent to the data bus (2) as the sending signal SD.

[Problem to be solved by the invention]

In the conventional bus sending circuit configured as described above, other circuits that receive the sending circuit SD via the data bus (2) may cause a signal identification error. This will be explained using FIG. 6. Sending instruction control signal co
is at a significant "L" level, the sending signal SD is sent out during the enable period t of the bus driver gate (8), and at the end of this enable period tE, the sending signal SD is sent out at the bus driver gate (8).
) is in a high impedance state. Generally, when all bus driver gates connected to the data bus (2) are in a high impedance state, the level of the data bus (2) is determined and pulled up with a pull-up resistor (3) to lower the impedance. This data bus (2) is maintained at a stable "H" level.

However, like the sending signal SD shown in FIG.
During the period when this is at the “Yes” level, the transmission instruction control signal C
0 enable period 1. Once this is completed, the level gradually increases with a time constant determined by the pull-up resistor (3), the stray capacitance of the bus sending board circuits (1a) to (1d), etc. On the other hand, on the side receiving the sending signal SD on the data bus (2), the threshold value V? for determining whether to process the sending signal SD? ? +, and it takes a voltage rise time tTH for the level of the data bus (2) to rise to the threshold value VTH, the processing time of the sending signal SD is extended by this amount.

However, if the receiving circuit that receives the sending signal SD has a circuit configuration that processes data on the condition that the level of the data bus (2) is ``L'', an error may occur in identifying an insignificant signal as a significant signal. There was a problem with it being stored away.

Note that lowering the resistance value of the pull-up resistor (3) in order to shorten the voltage rise time tTH would increase power consumption and was not practical.

This invention has been made to solve the above problems, and is a bus transmission system that can prevent a receiving circuit that receives transmission signals on a data bus from erroneously identifying an unreasonable signal as a significant signal. The purpose is to obtain a circuit.

(Means for Solving the Problem) The bus sending circuit according to the present invention calculates the logical sum of the sending data and the sending instruction control signal, makes the sending data valid only during the significant period of the sending instruction control signal, and makes the sending data valid during the period other than this. is a first gate circuit that generates sending data that has a logic level of "H" or "L" depending on whether the data bus is pulled up or pulled down, and the propagation delay of this first gate circuit. a delay circuit that delays a transmission instruction control signal by a predetermined value longer than time, and a significant period of the signal output from this delay circuit, and outputs the transmission data output from the first gate circuit onto the data bus. and a second gate circuit.

[Effect]

In this invention, sending data is valid only during the significant period of the sending instruction control signal, and during other periods, sending data is generated at a logic level depending on whether the data bus is pulled up or pulled down. Since this sending data is sent to the data bus during the valid period of the exit instruction control signal delayed by the circuit, the data bus is pulled up for a predetermined time after sending out the valid sending data Since a "L" level signal is added to each data bus whose "level signal has been pulled down," the level of the data bus can be determined early, thereby preventing identification errors in the receiving circuit that receives the data. be able to.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, the same reference numerals as in FIG. 4, which shows the conventional bus sending circuit, indicate the same elements. And (10a) other than these.

(10b) is the bus sending circuit board (la), (l
The bus sending circuit board corresponding to b), (11) is the gate (
7) and the output enable terminal OE of the bus driver gate (8), the output of the gate (7),
That is, the transmission instruction control signal C0 is transmitted for a predetermined time t. (12) is a gate that inverts the level of the sending data SD0; (13) receives the inverted data SDO of gate (12) from one side; gate (7); This is a NOR gate which takes the transmission instruction control signal Co of 1 as the other input, takes the negative OR of the two, and applies the result to the gate (8).

The operation of this embodiment configured as described above will be explained below.

First, when the address signal ADR3 transmitted via the address bus (4) matches the card address internally set in the address-multiple-sheet output circuit (6), this address-multiple-sheet output circuit (6) outputs an address match signal AE. The level of this address match signal AE is inverted at the gate (7) and outputted as the sending support control C0.

Next, the level of the sending data SDo is inverted by a gate (12), and the inverted data SDO is applied as one input of a NOR gate (13), and the other input of this NOR gate (13) is a sending instruction control signal C0. is added. By doing this, the output of the NOR gate (13) is held at the "L" level when the transmission instruction control signal C0 is at the insignificant "H" level, and when the transmission instruction control signal C0 is at the significant "L" level. , sending data SDI equal to sending data SDO is manually input to the bus driver gate (8).

On the other hand, the sending instruction control signal C0 is delayed by a predetermined time tn in the delay circuit (11), and the sending instruction control signal C1
is applied to the output enable terminal OH of the bus driver gate (8). As a result, the sending data SD,
However, during the significant period of the sending instruction control signal Co, the data bus (2) is sent from the bus driver gate (8) as the exit signal SD.
) is sent.

The above-mentioned relationship of signal transmission will be explained in detail with reference to the time charts of Fig. M2 and Fig. 3.

As shown in FIG. 2, for example, a 2-bit address signal ADRSa is transmitted through an address bus (4).

ADR3b is the bus sending circuit (10a), (10b)
address signal ADH5a is “H”.
Assuming that the address signal ADRSb is at the "L" level, only the address-several output circuit (6) of the bus sending circuit (10a) detects that it matches the card address and sends an address match signal at the "H" level. Outputs AE.

A gate (7) inverts this address-match signal AE and applies a transmission instruction control signal C6 to a delay circuit (11) and a NOR gate (13).

When the transmission instruction control signal Co is applied to the NOR gate (13), as described above, the transmission data SDO is inverted during the significant "L" level period and the transmission data SD is outputted, and conversely, Unreasonable data that continues at "L" level is output during a period of "H" level which becomes unreasonable.

On the other hand, the delay time t□ of the delay circuit (11) is slightly larger than the time 1h, which is approximately equal to the voltage rise time tTH described in the conventional device, and the delay time t of the NOR gate (12) is
If it is NOR, it is set as t (-+H'F th+ t NOR" (1).

Therefore, t is below the output enable terminal τ of the bus driver gate (8). The transmission instruction control signal C1 delayed by the time , is added, but the significant data of the transmission data SD is delayed by the propagation delay time tNOR of the NOR gate (13), so that the significant data of the transmission data SD, As can be seen, the output instruction control signal C4 delayed by the time th is applied to the output enable terminal OE. This means that the significant data of the sending data SD is inverted via the bus driver gate (8) and the significant data of the data bus (SD) is inverted.
2), after sending out the sending instruction control signal C1 for the th dark period.
The significant time continues, and the meaningless data (L level) after the significant data of the sending data SD is inverted by the bus driver gate (8) and becomes "H" on the data bus (2).
Sends a level signal.

That is, as shown in FIG. 3, after sending the significant data of the sending data SD to the data bus (2), the meaningless data is sent for 1 hour, and the th dark immediately after the significant state of the sending signal SD ends. In this configuration, an "H" level signal is sent out on the data bus (2) at different times.

Thus, according to this embodiment, when the application of the output enable signal is finished, the data bus (2)
“H” as “H” impedance from “L” level
The rise time tTH until the level is determined can be shortened, and the rise time tTH can be reduced depending on the increase or decrease of stray capacitance due to the number of boards, the size of the resistance value of the pull-up resistor, etc.
Even if TH changes, it is possible to prevent the receiving circuit from making a recognition error.

In the above embodiment, the case where the data bus (2) is pulled up is explained, but when the data bus (2) is pulled down, the sending instruction control signal C0
The sending data SDI is all at “H” level during the idle period.
By using a gate circuit that generates , it is possible to shorten the falling time tTH until the data bus is determined from the "H" level to the L level, as described above.

Furthermore, in the above embodiment, a bus driver gate that inverts the input data and outputs it to the data bus is used, but if a bus driver gate that outputs the input data level as it is to the data bus without inverting it is used, the sending The circuit may be configured so that the output data levels corresponding to the unreasonable period of the support control signal C0 are logically reversed.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, the send data is valid only during the significant period of the send instruction control signal, and during other periods, the send data is generated at a logic level corresponding to the level of the data bus. On the other hand, since this sending data is sent to the data bus during the valid period of the sending instruction control signal that is delayed by a predetermined amount, it is possible to respond to the fixed level of the data bus for a certain period of time after sending out the valid sending data. As a result, the level of the data bus can be determined at an early stage, and data identification errors in the receiving circuit that receives the data can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIGS. 2 and 3 are time charts for explaining the operation of the same embodiment, and FIG. 4 is a circuit diagram showing a conventional bus sending circuit. The circuit diagram shown in Figure 5 is a time chart for explaining the operation of this bus sending circuit, and Figure 6 is a data waveform diagram for explaining the problems of the prior art. (2)...Data bus, (3), (5)...Pull-up resistor, (4)...
・Address bus, (6)... Address-number configuration circuit, (7), (12)... Gate, (8)... Bus driver gate, (10a), (10b)... Bus Sending circuit board, (11)...Delay circuit, (13)...NOR gate. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] An address signal is received, a transmission instruction control signal that is valid for a predetermined period of time is generated from this address signal, and the transmission data is pulled up (
In a bus sending circuit that sends data onto a data bus that has been pulled down (or pulled down), the sending instruction control signal and the sending data are logically summed, and the sending signal is made valid only during the significant period of the sending instruction control signal, and other than that, the sending signal is valid only during the significant period of the sending instruction control signal. During the period, the first gate circuit that generates logic level "H" (or "L") data transmits the transmission instruction control signal for a predetermined value longer than the propagation delay time of the first gate circuit. The present invention is characterized by comprising a delay circuit that delays a signal, a significant period of a signal output from the delay circuit, and a second gate circuit that creates data output from the first gate circuit on the data bus. bus transmission circuit.