JPH01220511A - Pulse generation circuit - Google Patents

Abstract

PURPOSE:To always generate a pulse with constant width and with fast responsiveness even for the fluctuation of a source voltage or temperature change by operating all of the elements of an emitter follower, a constant current circuit, and a current mode logic circuit in an unsaturated current area. CONSTITUTION:When the comparators of transistors TrQ14 and Q15 perform switching operations, the change of the collector voltage of the TrQ14 at the time of changing the voltage Va with a change rate (alpha) can be expressed as {Va(1+alpha)-VBE(Q20)}.R9/(R15+R16). Meanwhile, when a circuit consisting of a diode-connected TRQ21 and a variable resistor VR is remarked and it is assumed that the intermediate terminal part of the variable resistor VR is set at resistance values RV2 and RV1, the base voltage of a TrQ6 goes to {Va(1+alpha)-VBE(Q21)}.RV2/RV1+RV2). Here, assuming VBE(Q20)=VBE(Q21) =VBE, the collector voltage of the TrQ14, that is, the base voltage of a TrQ12 and that of the TrQ6 are set at an irrelevant state since the fluctuation of the power source and the temperature change of the VBE of the TR can be negated with each other.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is based on the rise or fall time of a wide reference pulse signal as a pulse signal used when performing digital signal processing or analog signal switching. Constant pulse time width.

This invention relates to a pulse generation circuit for generating sharp pulses.

2. Description of the Related Art Conventionally, a circuit shown in FIG. 3 has been constructed and used using logic circuit means. Hereinafter, the operation of the circuit diagram in FIG. 3 will be explained together with the operational circuit diagram in FIG. 4.

When a reference pulse having a waveform like signal a is applied to the input terminal 1, a pulse output having a waveform like signal a appears on the output line 3 of the inverter 2.

Furthermore, the signal S is applied to another inverter 4, and a pulse output having a waveform like the signal C is obtained on its output line 5. When this signal C is passed through a time constant circuit composed of a variable resistor 6 and a capacitor 7, a delayed pulse like the signal d is obtained on the signal line 8. As shown in the figure, the pulse of
ND) When applied to the gate 9, a pulse output with a negative time width as shown by the signal e is obtained on the output line 10. Therefore, signal a
A negative pulse with a wide time width can generate a pulse with a narrow time width such as a signal e based on its fall time.

Problems to be Solved by the Invention Here, the NAND gate 9 has a logic that becomes low level only when both of its two gates become high level.
The threshold voltage VIH at a high level generally has temperature characteristics and increases with temperature. Therefore, in the case of a signal with a steep rise, the threshold voltage V
Although there is no time difference due to IH, in the case of the waveform shown in signal d, the threshold voltage V! The pulse time width of the output pulse signal e of the NAND gate 9 becomes PWI or PW2 due to the old or VIH2, and the time width changes depending on the temperature.

Further, when the power supply voltage of this logic circuit is different, the time width of the output pulse of the signal e also changes. That is, if we consider the case where the power supply voltage rises in the circuit described above, the signal shown in FIG. 4 will be generated.

The high level of each waveform c and e increases by a value approximately equal to the value at which the voltage was higher than before, and the variable resistor 6 and capacitor 7
The voltage applied to the time constant circuit consisting of becomes higher. The time constant T of the time constant circuit is T=C(F>・R(Ω) seconds), where the resistance value of the variable resistor is R2 and the value of the capacitance is C, so the signal d
The response waveform of is shown by a two-dot chain line, and since the time at which it crosses the threshold voltage V (old or V IH2) is different, the pulse output time width of signal e (PWI or p
y2 will be different. Furthermore, when a time width of several tens of ns is required, it is naturally necessary that the rise and fall times be fast, but this poses a problem with ordinary logic circuits, and high-speed logic circuit means, such as Schottky type TTL, are required. It is necessary to use

As mentioned above, in the conventional example, the time width of the generated pulse changes depending on the temperature and power supply voltage, and in applications that require high-speed rise and fall, it is possible to integrate other linear circuits into one chip using the normal diffusion process. There was a major problem in that high-speed operation was not possible when integrated.

Means for Solving the Problems The present invention includes a waveform shaping circuit that forms a constant amplitude pulse synchronized with a reference input pulse signal, and a constant current active circuit and a capacitor loaded in parallel on the output of this waveform shaping circuit. An emitter follower is connected, and the capacitor is charged and discharged by the emitter follower and the constant current active circuit, and a comparison circuit compares a preset voltage or a voltage set by the variable adjustment circuit with the terminal voltage of the capacitor. According to the present invention, all elements of the emitter follower, constant current circuit, and current mode logic circuit can be operated in an unsaturated current region, and high-speed response is achieved. There is also power supply voltage fluctuation,
It is possible to always generate pulses with a constant width even when the temperature fluctuates.

FIG. 1 shows a specific circuit example of the pulse generation circuit of the present invention.
A pulse having a preset constant time width is output to the output terminals P1 and R2 based on the fall time of the reference pulse supplied to the input terminal P3.

In order to achieve high-speed operation, logic element circuits are configured using constant current type unsaturated differential amplifiers, thereby eliminating the need for special diffusion processes such as the Schottky process (integration on the same chip as linear circuits). In Fig. 1, the resistors R11, RI2, R13
TR14 and transistor Q 17 , Q +a *
Q +s and resistance RI5. RIB and transistor Q20. The circuits consisting of Q21 each have a voltage source v,
, Vb and current source 1c (020>) are created.

Here, the time width t! as shown in signal A in FIG. 2! When a reference pulse input of Q1 is applied to terminal P3, transistor Q1
4. Q10. It is compared with voltage Vb by a differential comparison circuit consisting of Q16 and resistors Rs and R+o, and is applied to the collector of transistor Q14 as signal B in FIG.

A pulse with a constant amplitude determined by the collector current I C (Q16) of the transistor QCs and the resistor R9 is output. This signal B is transferred to transistor QI2. By amplifying the current through an emitter follower composed of Q+3 and resistor R8, and connecting a capacitor CI between the connection point of the emitter of transistor Q17J and the collector of transistor QI3 and the ground point,
The voltage across this capacitor CI generates a voltage waveform like signal C in FIG. That is, when the base voltage of the transistor QI2 becomes low, the previous high voltage is stored in the capacitor IC+, so the transistor Q12 is cut off. Therefore, the voltage stored in the capacitor is discharged at a constant current by the collector current of constant current source transistor Q13.

Next, if the base voltage of transistor QI2 becomes high,
Transistor QI2 now operates as an emitter follower and quickly charges capacitor C+. As a result of the above operations, the waveform of signal B in FIG. 2 becomes like signal C in the same figure as the terminal voltage of capacitor C+, and transistor Q+o
connected to the base of

Transistor Qs+ Q+o, Q++ and resistor Rs,
The circuit composed of R6eR7 is a second comparator, and the voltage set by the variable resistor VR that adjusts the output pulse width is transferred to the transistors Q8. The reference voltage applied to the base of transistor Q9 is compared with the voltage waveform applied to the base of transistor Q+o, and the signals shown in FIG. 2 are applied to each transistor Q+o and Qs, respectively. Generates pulse output.

A circuit composed of transistors QI-Qs and resistors R1 to R3 is an emitter-coupled logic (ECL) for performing signal processing using the aforementioned signals A, D, and E. This ECL circuit is configured such that the base of transistor Q1 is at high level, the base of transistor Q2 is at low level, and only when the base of transistor Q4 is at low level, output terminal P1 is at low level and P1 is at high level. As can be seen from the above description, pulse output signals H and I having a set time width T2 can be obtained from the fall time of the input reference pulse. Next, it will be explained that, according to the present invention, the time width of the pulse output set with respect to power supply voltage (Vcc) and temperature fluctuations is low. To simplify the explanation, ignoring the base current of each transistor, when the comparators of transistors Q and Q15 switch, the collector voltage of transistor Q when voltage v3 changes at a rate of change α is: The change is (V
, (1+α)-Vsg(uo)iRs/(R+s+R+
s). On the other hand, focusing on the circuit of the diode-connected transistor Q21 and the variable resistor VR, if the intermediate terminal portion of the variable resistor VR is set to the respective resistance values of RVle and RV2, the base voltage of the transistor Q6 is IVa ( 1+α) Vi+E(B1)i Rv+/(
Rv+ +RV2) Tonal o Kokote VsE<o2o)
=Vne<o2+)=VsE, then transistor Q
The two collector voltages, ie, the base voltage of transistor Q12 and the base voltage of transistor QB, compensate each other for power supply fluctuations and transistor VBE temperature changes and become independent. Transistor Qs* of the second comparator configuration
Q+.

The above voltages are applied to the base of the transistor Qe, respectively.
, Qu are supplied through the emitter followers, so the relationship between the two does not collapse. Since the current of the constant current discharge transistor Q+3 changes in proportion to the current of the transistor 020, the capacitance C1 and the transistor Q13
The time constant is determined by TO=C-R9, and is unrelated to the power supply voltage and the temperature characteristics of vag.

As described in detail, according to the present invention, all the elements used are ECL circuits that operate in unsaturated state, so the storage time of the transistor is very short, and the rise and fall characteristics are good without using a special high-speed process. This has the great effect of making it possible to create a pulse generator that can generate pulses with a constant pulse duration regardless of power supply voltage fluctuations and temperature fluctuations.

[Brief explanation of the drawing]

Fig. 1 is a specific circuit diagram of an embodiment of the present invention, Fig. 2 is an operation waveform diagram of each part of the circuit of the embodiment, Fig. 3 is a circuit diagram of a conventional pulse generation circuit, and Fig. 4 is a circuit diagram of the conventional example. FIG. 3 is an operation waveform diagram for explaining the operation of the example circuit. Q1~Q2+...Transistor, R1~RIB
...Resistor, C1...Capacitor. Name of agent: Patent attorney Toshio Nakao and one other person Figure 2-47rhi Figure 3 Figure 4

Claims (1)

[Claims] A waveform shaping circuit that forms a pulse with a constant amplitude in synchronization with a reference input pulse signal is connected to the output of this waveform shaping circuit, and an emitter follower in which a constant current active circuit and a capacitor are loaded in parallel, and the charging and discharging of the capacitor is performed. is performed by the emitter follower and the constant current active circuit, a preset voltage or a voltage set by the variable adjustment circuit is compared with the terminal voltage of the capacitor, and the output of the comparison circuit and the input pulse signal are compared. A pulse generation circuit characterized by comprising a current mode logic circuit that performs logic processing.