JPH01220521A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To minimize a gate delay time by forming an internal gate circuit format as a logic circuit consisting of only a CMOS transistor at a small load, and attaching the output stage of a bipolar transistor at a large load. CONSTITUTION:Since the wiring capacitance of wiring 6 is as small as less than Cs in the internal gate 2 of an LSI chip 1, a 2-input NAND circuit by only a CMOS transistor is shown. Circuits shown in dotted line show a nonuse bipolar transistor 5 and a nonuse specific impedance element, and the diffusion processes for those circuits are completed, and the logic circuit consisting of only the CMOS transistor is formed by changing the wiring, and since the wiring capacitance of a gate 3 is as large as more than Cs, the 2-input NAND circuit on which the output stage by the bipolar transistor is attached is formed. When the wiring is extended in such way and fan out is increased and the load is increased, it is possible to reduce the dependency of the gate delay time for the load by attaching the output stage consisting of the bipolar transistor with high driving capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device in which a CMOS transistor and a bipolar transistor are formed on the same chip; in particular, it relates to a gate array type semiconductor integrated circuit.

[Conventional technology]

Conventionally, in this type of gate array type LSI, all internal gates are composed of a logic circuit using CMOS type transistors and an output stage using bipolar type transistors.

FIG. 3 is a circuit diagram of a gate array type LSI chip for explaining an example of such a conventional technique.

As shown in FIG. 3, this LSI chip 11 is a CMO
It is a gate array type LSI in which an S type transistor and a bipolar type transistor are formed on the same chip, and it is a CMO
The logic circuit section of the S-type transistor has an internal gate 13 forming a two-way NAND circuit, and these are connected by a wiring 16, while a certain impedance is connected between the P-channel MOS (Run Lister) and the N-channel MOS transistor. A specific impedance circuit 14' is connected between the N-channel MoS transistor and the ground. Furthermore, internal gate 13
The output stage of is configured by an npn bipolar transistor 15 in the form of a totem pole circuit.

FIG. 4 is a characteristic diagram of gate delay time with respect to load capacitance of the LSI chip shown in FIG. 3.

As shown in FIG. 4, reference numeral 17 represents the delay characteristic of an internal gate composed of a CMOS transistor, and reference numeral 18 represents a delay characteristic of a bipolar/CMO3 mixed internal gate. When the load capacitance is from 0 to C5, the delay time (tpa) is longer when using only the internal gate of a CMOS transistor.
When the load capacity is small and the load capacitance is large, that is, C3 or higher, the bipolar/CMO3 mixed internal gate has a shorter delay time.

[Problem to be solved by the invention]

When the load capacitance is small, the internal gate of the above-mentioned conventional gate array type LSI in which a CMOS transistor and a bipolar transistor are formed on the same chip is more efficient than a gate circuit using only a CMOS transistor. However, the gate delay time is slow, and the power consumption is large.

An object of the present invention is to provide a semiconductor integrated circuit device that reduces gate delay time depending on the magnitude of load capacitance and consumes low power.

[Means to solve the problem]

The semiconductor integrated circuit device of the present invention, that is, the gate array LSI uses a logic circuit consisting only of CMOS type transistors for the internal gate when the load such as wiring capacitance and fanout is small, and the load of wiring capacitance and fanout number is reduced. When the size is large, the internal gate is composed of a CMOS type transistor and a bipolar type transistor.

In particular, the internal gates of only CMOS transistors and C
It is possible to change the connection between the internal gate of a MOS transistor and the internal gate to which a buffer circuit of a bipolar transistor is added as an output stage using contacts and wiring depending on the load condition.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an LSI chip showing a first embodiment of the present invention.

As shown in FIG. 1, 1 is a gate array LSI formed on a substrate by a mixture of CMOS transistors and bipolar transistors, and the internal gate 2 in this LSI chip 1 has a wiring capacitance of wiring 6 of less than C5. The small image shows a two-man NAND circuit formed only with CMOS transistors. The circuit shown by the dotted line in this internal gate 2 shows an unused bipolar transistor 5 and a certain unused impedance element 4, but these circuits have already been completed up to the diffusion process, and the wiring cannot be changed. This forms a logic circuit consisting only of CMOS type transistors. In addition, since the wiring capacitance of the wiring 7 in the internal gate 3 is thick and exceeds Cs, a two-man NAND circuit 3 is formed by adding an output stage constituted by a bipolar transistor to the internal gate circuit of a CMOS transistor. . As with the internal gate 3, when the wiring length increases and the fan-out increases, resulting in a large load, adding an output stage using bipolar transistors with high load driving ability reduces the gate delay time for the load. Dependency is reduced.

FIG. 2 is a circuit diagram of an LSI chip showing a second embodiment of the present invention.

As shown in FIG. 2, the internal gate 2 of the LSI deep 1 is a two-man NAND gate formed only with CMOS transistors because the load capacitance of the wiring is small, and the internal gate 3 is connected to the wiring and fan-out. Since the load on the number is large, a two-man power NAND gate is shown in which an output stage composed of bipolar transistors is added to the internal gate circuit of a CMOS transistor.

Furthermore, when the load capacitance is large, the output buffer circuit 8 is an internal gate configured by connecting a bipolar transistor 9 in parallel to a bipolar transistor in the output stage, and an output pad 10 connected to the output buffer 8.
1 shows a pad for taking out a signal to the outside of an LSI chip 1 in which a CMOS transistor and a bipolar transistor are formed on the same chip.

In this way, in this embodiment, the internal gate circuit consisting only of CMOS transistors is more likely to be bipolar depending on the load condition.
Noting that the gate delay time is sometimes faster than that of the CMO3 mixed internal gate, the configuration is such that the connection can be changed depending on the load condition.

〔Effect of the invention〕

As explained above, the semiconductor integrated circuit device of the present invention includes
The circuit format of the internal gate is a logic circuit with only CMOS type transistors when the load is small, and a CM type transistor when the load is large.
By adding a bipolar transistor output stage to the OS transistor logic circuit, the gate delay time of the internal gate can be minimized, and the internal gate formed only with CMOS transistors is different from the conventional one. This has the effect of lower power consumption than the bipolar CMO8 type internal gate.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a game I array type LSI chip showing a first embodiment of the present invention, FIG. 2 is a circuit diagram of an LSI chip not showing a second embodiment of the present invention, and FIG. A circuit diagram of a gate array type LSI chip showing an example of the conventional technology, Fig. 4 is the same as Fig. 3.
FIG. 3 is a characteristic diagram of gate delay time with respect to load capacitance of the LSI chip shown in the figure. 1...LSI chip, 2...Internal gate of CMOS type transistor only, 3...Internal gate consisting of CMOS) run lister and bipolar transistor (normal internal gate), 4...Unused impedance circuit, 5
... Unused bipolar transistor, 6... Wiring with small load capacity, 7... Wiring with large load capacity, 8
... Output buffer, 9... Bipolar transistor for additional output stage, 10... Output pad. Agent Patent Attorney Oto Uchihara

Claims (1)

[Claims] In a semiconductor integrated circuit device having a CMOS transistor and a bipolar transistor on the same chip,
When the load of wiring capacitance and fan-out number is small, use a logic circuit with only CMOS type transistors for the internal gate,
A semiconductor integrated circuit device characterized in that when the load of wiring capacitance and fan-out number is large, the internal gate is formed by a CMOS type transistor and a bipolar type transistor, and the connection can be changed using contacts and wiring depending on the load condition. .