JPH01226285A - Digital storage device for analog signal - Google Patents

Abstract

PURPOSE:To use the circuit element of low processing frequency by providing a first storage device to A/D convert and store an analog signal according to the rise of a sampling clock, and a second storage device to A/D-convert and store it according to the fall of it. CONSTITUTION:A first A/D conversion circuit 2 performs the A/D conversion of a video signal according to the rise of the sampling clock of a positive phase, and an even number-th digital signal is stored in a first picture memory element 6. Besides, a second A/D conversion circuit 3 performs the A/D conversion of the same video signal according to the rise of the sampling clock of a negative phase, and an odd number-th digital signal is stored in a second picture memory element 7. Then, these even number-th and odd number-th digital signals are written in the respective memory elements 6, 7 in the turn from a head address according to an address signal from a memory control circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is a method for converting an analog signal into a digital one for A/D conversion and storage, such as an image memory device that stores a video signal for one screen. It is related to storage devices.

[Conventional technology]

VTR [video tape recorder]
FIG. 3 shows a conventional image memory device used in cameras and television receivers.

The N'rSC video signal is input to a sampling clock generation circuit 21 and an A/D conversion circuit 22. The sampling clock generation circuit 21 generates vertical and horizontal synchronization signals of the input video signal and the memory control circuit 23.
A sampling clock for one screen (one field or one frame) is generated based on the reference signal from.

This sampling clock is used by the A/D conversion circuit 22.
sent to. Thereby, the A/D conversion circuit 22 samples the video signal based on this sampling clock, quantizes it into 6 bits, and converts it into a digital signal. This digital signal is sent to the image memory element 24 in parallel, 6 bits at a time.

At this time, the memory control circuit 23, based on the clock from the sampling clock generation circuit 21,
An address that advances by one address from the first value is sent to this image memory element 24. Therefore, in the image memory element 24, A/
The 6-bit digital signal sent from the D conversion circuit 22 is sequentially stored in this address.

When reading out one screen worth of digital signals stored in this way, the memory control circuit 23 again reads the address that advances one address at a time from the first value to the image memory element 24.
Send sequentially to Therefore, the launch circuit 25 sequentially latches the digital signals at each address of the image memory element 24 based on the control signal from the memory control circuit 23 and sends them to the decoder circuit 26. The decoder circuit 26 decodes the sent 6-bit digital signal and restores it to an analog video signal. The video signal output from this decoder circuit 26 is then
The image is sent to the RT display device 27 and displayed.

Such an image memory device is a TV-? 'Used for still display and image quality improvement in VTRs, etc.

[Problem to be solved by the invention]

Here, the horizontal scanning frequency of the video signal in the NTSC system is 15.734 kHz. However, the video signal for CRT display in personal computers has a horizontal scanning frequency of 31.5kHz, which is twice this frequency.
Those are the mainstream.

For this reason, when attempting to store video signals for this personal computer using the configuration of a conventional image memory device, all circuit elements including the A/D conversion circuit 22, image memory element 24, and peripheral circuits must be stored. needs to be processed at a high frequency.

Therefore, conventionally, the higher the frequency of the sampling clock required by the analog signal to be stored, the more
Since it is necessary to use a circuit element with a high processing frequency corresponding to this, there is a problem that the apparatus becomes expensive.

[Means to solve the problem]

In order to solve the above problems, an analog signal digital storage device according to the present invention includes a sampling clock generation circuit that generates a sampling clock in an analog signal digital storage device that A/D converts and stores an analog signal. The first step is to A/D convert the analog signal based on the rising edge of this sampling clock. an A/D converter circuit, a first storage device that stores the digital signal output from the first A/D converter circuit, and a second A/D converter that A/D converts the analog signal based on the falling edge of the sampling clock. a conversion circuit, a second storage device that stores the digital signal output from the second A/D conversion circuit, and a readout device that alternately reads out the digital signals stored in the first storage device and the second storage device in the writing order. It is characterized by having a control circuit.

[For production]

The sampling clock generation circuit generates a square wave sampling clock. This sampling clock uses the rising and falling edges of the pulse, so the duty factor is approximately 0. It must be a square wave with a value of 5.

The first A/D conversion circuit converts analog signals such as video signals into A/D converters based on the rise of this sampling clock.
Convert. Then, the A/D converted digital signal is
The information is sequentially written and stored in the first storage device.

The second A/D conversion circuit A/D converts the same analog signal based on the falling edge of the sampling clock. Therefore, the sampling in the second A/D conversion circuit is
This is performed at approximately the center timing of each sampling interval in the first A/D conversion circuit. Therefore, the analog signal is sampled at twice the frequency of the sampling clock by the first A/D conversion circuit and the second A/D conversion circuit. The digital signal A/D converted by the second A/D conversion circuit is
The information is sequentially written and stored in the storage device.

Note that if the second A/D conversion circuit inverts the sampling clock generated by the sampling clock generation circuit and performs sampling based on a sampling clock of opposite phase, the second A/D conversion circuit can reduce the pulses used in the first A/D conversion circuit. The same A/D conversion circuit that performs sampling at the rising edge can be used. That is, the second A in this case
The /D conversion circuit is composed of a circuit (which may be an inverter circuit) that generates a sampling clock of opposite phase and an A/D conversion circuit that performs sampling at the rising edge of a pulse. Furthermore, in the case of using two A/D conversion circuits that perform sampling at the falling edge of a pulse, the first A/D conversion circuit may use a sampling clock having an opposite phase.

Also, see Section 1, 1. Since the a device and the second 4) 1 device are controlled individually, the write process is performed at the same processing frequency as the sampling clock.

The digital signals stored in the first storage device and the second storage device in this manner are alternately and sequentially read out by the readout control circuit. In each storage device, the digital signals stored at the respective addresses are read out in the order in which they were written.

By alternately connecting and combining the digital signals from these storage devices, the read control circuit can output a digital signal that is the same as the original analog signal sampled with twice the sampling clock.

In this case as well, if the digital signals read from each storage device are lied once and then taken out alternately and connected, the read processing in each storage device can be performed at the same processing frequency as the sampling clock. be able to.

Therefore, in the digital storage device of the present invention, processing is performed based on a frequency that is half of the sampling clock originally required for the analog signal to be stored, so circuit elements with a low processing frequency can be used. .

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

In this embodiment, the horizontal scanning frequency according to the NTSC system is 15.
．． An image memory device that can store one screen worth of a 734 kHz video signal and a 31.5 kHz horizontal scanning frequency video signal used in a personal computer or the like will be described.

The video signal is sent to the horizontal scanning frequency detection circuit 1 and the first A/
The signal is sent to a D conversion circuit 2 and a second A/D conversion circuit 3. The horizontal scanning frequency detection circuit 1 separates vertical and horizontal synchronization signals from the input video signal, and
The horizontal scanning frequency of this video signal is 15.734 kH
z or 31.5kHz. The output terminals of the vertical and horizontal synchronizing signals separated by the horizontal scanning frequency detection circuit 1 are connected to the sampling clock generation circuit 4. In addition, this horizontal scanning frequency detection circuit 1
The output terminal of the discrimination signal discriminated by is connected to the memory control circuit 5. The memory control circuit 5 is configured to send a reference signal to the sampling clock generation circuit 4 based on the input discrimination signal. The sampling clock generation circuit 4 generates a square-wave positive-phase sampling clock and a negative-phase sampling clock based on the reference signal and the vertical and horizontal synchronization signals.

The negative phase sampling clock is an inversion of the positive phase sampling clock. This sampling clock generation circuit 4 is also configured to send a clock signal having the same frequency as these sampling clocks to the memory control circuit 5. Based on this clock signal, the memory control circuit 5 reads 1 from the first value.
It generates an address signal that advances one address at a time, and control signals for a first latch circuit 8, a second launch circuit 9, and a changeover switch 10, which will be described later.

The output terminal of the positive phase sampling clock generated by the sampling clock generation circuit 4 is connected to the clock input of the first A/D conversion circuit 2. Further, the output terminal of the sampling clock of opposite phase is connected to the clock input of the second A/D conversion circuit 3. Each A/D conversion circuit 2 and 3 is a circuit that performs A/D conversion by sampling the input video signal and performing 6-bit quantization at the rising timing of these positive-phase and negative-phase sampling clocks. It is. Therefore, the video signal is sampled at substantially twice the frequency of this sampling clock. These A/D conversion circuits 2・
The 6-bit parallel output terminals of the digital signals A/D converted in step 3 are connected to the first image memory element 6 and the second image memory element 7, respectively.

The image memory elements 6 and 7 are storage elements each capable of storing one screen worth of digital signals of video signals in the NTSC system. The memory control circuit 5
The respective output terminals of the address signals generated are connected to the address inputs of these image memory elements 6 and 7, respectively. Therefore, each image memory element 6, 7 sequentially writes and stores the input 6-bit digital signal based on this address signal. The 6-bit parallel output terminals of these image memory devices 6 and 7 are connected to a first launch circuit 8 and a second launch circuit 9, respectively.

Note that the input and output of these image memory elements 6 and 7 can also be in a path format.

The launch circuits 8 and 9 are circuits that each latch a 6-bit digital signal. Each output terminal of the control signal of the first launch circuit 8 and the second launch circuit 9 generated by the memory control circuit 5 is connected to the control terminal of these launch circuits 8 and 9, respectively. Therefore, each launch circuit 8, 9 activates the image memory element 6, 7 at the rising timing of these control signals.
Latch the digital signal read from. The 6-bit parallel output terminals of these launch circuits 8 and 9 are connected to two switching inputs of a changeover switch 10, respectively.

The changeover switch 10 is a circuit that switches between two 6-bit parallel inputs and outputs the selected one. The output terminal of the control signal of the changeover switch 10 generated by the memory control circuit 5 is connected to the control terminal of the changeover switch 10.

Therefore, based on this control signal, the changeover switch 10 outputs the latched digital signal to the first launch circuit 8 when this control signal is at "H" level, and outputs the digital signal latched to the first launch circuit 8 when this control signal is at "L" level. The digital signal latched by the circuit 9 will be output. A 6-bit parallel output terminal of this changeover switch 10 is connected to a decoder circuit 11.

The decoder circuit 11 is a circuit that sequentially decodes input digital signals and restores them to analog video signals. The output terminal of this decoder circuit 11 is connected to a CRT display device 12.

It should be noted that the changeover switch 10 is configured to switch between "H" level and "L" level in a control signal having the same frequency as the sampling clock.
``When outputting a digital signal at a level, the decoder circuit 11 needs to perform decoding processing at twice the frequency of the sampling clock.

The CRT display device 12 is a device for displaying an input analog video signal on a CRT screen. Note that this CRT display device 12 is also configured to switch the horizontal scanning frequency according to the input video signal.

The operation of the image memory device having the above configuration will be explained based on FIG. 2.

The horizontal scanning frequency of the input video signal is 31.5kHz
If the horizontal scanning frequency detection circuit 1 is for a personal computer, the horizontal scanning frequency detection circuit 1 determines this and issues a determination signal to this effect to the memory control circuit 5.

The first A/D conversion circuit 2 performs A/D conversion of the video signal based on the rising edge of the positive phase sampling clock.

Therefore, when this video signal is sampled at twice the frequency of the sampling clock, the 0th, 2nd
Even-numbered digital signals such as the 4th, 4th, etc. are stored in the first image memory element 6. Also, the 2nd A/D
The conversion circuit 3 performs A/D conversion of the same video signal based on the rising edge of the sampling clock of opposite phase. Therefore, when this video signal is sampled at twice the frequency of the sampling clock, the first, third,
Odd-numbered digital signals, such as the fifth, etc., are stored in the second image memory element 7.

These even-numbered and odd-numbered digital signals are sequentially written into each of the image memory elements 6 and 7 from the top address based on the address signal from the memory control circuit 5, respectively. Note that each image memory element 6.
The address signals sent to the second image memory element 7 may have the same address, but since the writing timings are different, the phase of the one sent to the second image memory element 7 is delayed.

When reading out the digital signals stored in each of the image memory elements 6 and 7 in this manner, the memory control circuit 5 again issues an address signal that advances one by one from the first value, and the first launch circuit 8 and the second latch Each control signal for the circuit 9 and changeover switch 10 is generated. Second
The phase of the address signal sent to the image memory element 7 is delayed in the same way as in writing. First launch circuit 8
The control signal is a square wave with the same frequency as the sampling clock. Further, the control signal for the second latch circuit 9 is an inversion of the control signal for the first launch circuit 8.

Each of the launch circuits 8 and 9 performs a launch operation at the rise of these control signals. Further, the control signal for the changeover switch 10 is the one whose phase is delayed by 90 degrees from the control signal for the first launch circuit 8.

First, based on the address signal, the digital signals stored in each of the image memory elements 6 and 7 are read out alternately in the writing order. Then, based on the control signals of the launch circuits 8 and 9, the read digital signals are alternately latched in each of the launch circuits 8 and 9. Then, based on the control signal of the changeover switch 10, the latched digital signals are alternately and sequentially outputted from the changeover switch 10.

Therefore, for example, if the 0th digital signal is output when the control signal of the changeover switch 10 is at the "H" level, the first digital signal will be output when the control signal is at the next "L" level, and then again at the "H" level. When it becomes 2
The digital signal □ is output, and the digital signals □ are output sequentially in the order of sampling, so it is possible to obtain the same digital signal as when the original video signal is A/D converted at twice the frequency of the sampling clock. . Furthermore, the processing operations of each circuit up to this point are all based on the same processing frequency as the sampling clock.

The horizontal scanning frequency of the input video signal is 15.734k
If it is based on the NTSC system of llz, the horizontal scanning frequency detection circuit 1 determines this and issues a determination signal to this effect to the memory control circuit 5. Then,
This memory control circuit 5 always issues an "H" level control signal to the changeover switch 10 so that the first launch circuit 8 outputs only the latched digital signal. Further, the address signal with a delayed phase to the second image memory element 7 is no longer necessary, and the sampling clock generation circuit 4 also generates a sampling clock with an opposite phase to the second image memory element 7.
/No longer sent to the D conversion circuit 3. Therefore, in this case, it operates similarly to the conventional image memory device shown in FIG. - As described above, in the image memory device of this embodiment, all the circuits except the decoder circuit 11 and the CRT display device 12 are configured with the same low processing frequency as the sampling clock in the NTSC video signal. NTSC
It is possible to automatically determine and store not only the video signal of the system, but also one screen worth of video signal for a personal computer whose horizontal scanning frequency is doubled.

〔Effect of the invention〕

As described above, the analog signal digital storage device according to the present invention includes a sampling clock generation circuit that generates a sampling clock, and a sampling clock generation circuit that generates a sampling clock, and a sampling clock generation circuit that generates a sampling clock. a first A/D conversion circuit that A/D converts the analog signal based on the rising edge of the sampling clock; a first storage device that stores the digital signal output from the first A/D converting circuit; A second A/D converting the analog signal based on the
a D conversion circuit, a second storage device for recording the digital signal output from the second A/D conversion circuit, and a digital signal stored in the first storage device and the second storage device alternately in writing order. The structure includes a read control circuit for reading data.

As a result, the stored analog signal can be processed based on a frequency that is half of the sampling clock originally required, so circuit elements with a low processing frequency can be used.

Therefore, the digital storage device of the present invention can use an A/D conversion circuit and a storage device with a low processing frequency, so that the cost of the device can be reduced. Further, even when the analog signal requires sampling at a high frequency, the operating margin of the circuit is improved, so there is an effect that the reliability of the device can be improved.

[Brief explanation of the drawing]

1 and 2 show an embodiment of the present invention, in which FIG. 1 is a block diagram of an image memory device, and FIG. 2 is a time chart showing each signal waveform of the image memory device. FIG. 3 shows a conventional example, and is a block diagram of an image memory device. 2 is a first A/D conversion circuit, 3 is a second A/D conversion circuit, 4
1 is a sampling clock generation circuit, 5 is a memory control circuit, 6 is a first image memory element (first storage circuit),
7 is a second image memory element (second storage circuit).

Claims (1)

[Claims] 1. In an analog signal digital storage device that A/D converts and stores an analog signal, a sampling clock generation circuit that generates a sampling clock, and a first A/D converter that A/D converts the analog signal based on the rising edge of the sampling clock. /D conversion circuit and this first A/D conversion circuit.
The first one stores the digital signal output from the D conversion circuit.
a storage device, a second A/D conversion circuit that A/D converts the analog signal based on the falling edge of the sampling clock, and a second storage device that stores the digital signal output from the second A/D conversion circuit. A digital storage device for analog signals, comprising: a readout control circuit that alternately reads digital signals stored in the first storage device and the second storage device in the order in which they are written.