JPS5896338U - Polyphase A/D converter - Google Patents
Polyphase A/D converterInfo
- Publication number
- JPS5896338U JPS5896338U JP18941581U JP18941581U JPS5896338U JP S5896338 U JPS5896338 U JP S5896338U JP 18941581 U JP18941581 U JP 18941581U JP 18941581 U JP18941581 U JP 18941581U JP S5896338 U JPS5896338 U JP S5896338U
- Authority
- JP
- Japan
- Prior art keywords
- converter
- polyphase
- analog signal
- converts
- digital signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は高帯域のアナログ信号をデジタル信号に変換す
るＡ／Ｄ−回路のブロック図、第２図はこの考案のＡ／
Ｄ変換器のブロック配線図、第３図はクロック信号の波
形の二例を示すタイムチャート、第４図はこの適業のＡ
／Ｄ変換器を利用した高帯域のＡ／Ｄ変換回蕗ローロッ
ク図を示す。
図中、Ｃはコン具レータ、Ｃ１〜Ｃｎは比較器、Ｍ１〜
Ｍ４はメモリ、ＥＮ１〜ＥＮ４はエンコーダである。
−Figure 1 is a block diagram of an A/D circuit that converts high-band analog signals into digital signals, and Figure 2 is a block diagram of the A/D circuit of this invention.
The block wiring diagram of the D converter, Figure 3 is a time chart showing two examples of clock signal waveforms, and Figure 4 is the A of this application.
FIG. 6 shows a low-lock diagram of a high-band A/D conversion circuit using a /D converter. In the figure, C is a converter, C1 to Cn are comparators, and M1 to Cn are comparators.
M4 is a memory, and EN1 to EN4 are encoders.
−
Claims (1)
おいて、アナログ信号を量子化するコンパレータの後段
に、多相化したメモリと、その相数に対応したエンコー
ダを設け、アナログ信号を並列したデジタル信号に変換
することを特徴とする多相形Ａ／Ｄ変換器。In an A/D converter that converts an analog signal into a digital signal, a multiphase memory and an encoder corresponding to the number of phases are installed after the comparator that quantizes the analog signal, and a digital signal is created by parallelizing the analog signal. A polyphase A/D converter characterized in that it converts into.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18941581U JPS5896338U (en) | 1981-12-21 | 1981-12-21 | Polyphase A/D converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18941581U JPS5896338U (en) | 1981-12-21 | 1981-12-21 | Polyphase A/D converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5896338U true JPS5896338U (en) | 1983-06-30 |
Family
ID=30103323
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18941581U Pending JPS5896338U (en) | 1981-12-21 | 1981-12-21 | Polyphase A/D converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5896338U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01226285A (en) * | 1988-03-04 | 1989-09-08 | Sharp Corp | Digital storage device for analog signal |
-
1981
- 1981-12-21 JP JP18941581U patent/JPS5896338U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01226285A (en) * | 1988-03-04 | 1989-09-08 | Sharp Corp | Digital storage device for analog signal |
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