JPH01227128A - Liquid crystal display device - Google Patents
Liquid crystal display deviceInfo
- Publication number
- JPH01227128A JPH01227128A JP63053401A JP5340188A JPH01227128A JP H01227128 A JPH01227128 A JP H01227128A JP 63053401 A JP63053401 A JP 63053401A JP 5340188 A JP5340188 A JP 5340188A JP H01227128 A JPH01227128 A JP H01227128A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- gate
- liquid crystal
- electrode
- crystal display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Liquid Crystal (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は液晶表示装置に関し、特にＴＦＴアレイを用
いた液晶表示装置において、大面積化及び高解像度化を
行う際のゲート電極配線の断線欠陥、及びゲート電極配
線とソース電極配線との交差部分における短絡欠陥の低
減に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a liquid crystal display device, and particularly to a liquid crystal display device using a TFT array, in which disconnection defects in gate electrode wiring are prevented when increasing the area and increasing the resolution. , and reduction of short-circuit defects at intersections between gate electrode wiring and source electrode wiring.
液晶表示装置は通常２枚の対向基板の間に液晶などの表
示材料が挟持され、この表示材料に電圧を印加する方法
で構成される。この際、少なくとも一方の基板にマトリ
ックス状に配列した画素電極を設け、これらの画素を選
択的に動作させるために各画素毎にＦＥＴ（Ｔ！ｌ界効
果トランジスタ）等の非線形特性を有する能動素子を設
けている。A liquid crystal display device is usually constructed by a method in which a display material such as liquid crystal is sandwiched between two opposing substrates, and a voltage is applied to the display material. At this time, pixel electrodes arranged in a matrix are provided on at least one of the substrates, and in order to selectively operate these pixels, an active element having nonlinear characteristics such as an FET (T!L field effect transistor) is installed for each pixel. has been established.
従来のこの種の装置としては、第５図、第６図。Conventional devices of this type are shown in FIGS. 5 and 6.
第７図に示すようなものがあり、第５図は従来法により
形成した液晶表示装置のＴＦＴアレイの部分平面図ミ第
６図及び第７図はそれぞれ第５図のＤ−Ｄ’ 部及びＥ
−Ｅ’ 部の断面図である。殿において、１は透明絶縁
基板、２はゲート電橋及び配線、３はソース電極及び配
線、４はドレイン電極、５は画素電極、６はゲート！！
！縁膜、７は半導体層、８はパッシベーション膜、９は
遮光膜、１０はドレイン電極と画素電極とのコンタクト
部、１１は画素電極と同時形成したゲート配線である。As shown in FIG. 7, FIG. 5 is a partial plan view of a TFT array of a liquid crystal display device formed by a conventional method. E
-E' section is a sectional view. In the figure, 1 is a transparent insulating substrate, 2 is a gate bridge and wiring, 3 is a source electrode and wiring, 4 is a drain electrode, 5 is a pixel electrode, and 6 is a gate! !
! 7 is a semiconductor layer, 8 is a passivation film, 9 is a light shielding film, 10 is a contact portion between the drain electrode and the pixel electrode, and 11 is a gate wiring formed at the same time as the pixel electrode.
一般に、液晶表示装置等に用いられるＴＦＴアレイのゲ
ート電橋は、通常、耐熱性の高いＣｒ等の高融点金属が
用いられるが、大画面、高解像度化を行うには配線抵抗
による信号の減衰、遅れ等を防止するため、膜厚を厚く
し、低抵抗化を図る必要がある。しかし、膜厚を厚くす
るとＣｒ等の高融点金属は膜の応力のためにクラックな
どの発生確率が高（なる。また、高解像化、大画面化に
ともなう微細配線化、配線長の増大のためにゴミ等によ
るパターニング不良等による断線が発生し、歩留りの低
下を招くといった欠点がある。このような欠点を克服す
るため、従来の液晶表示装置のＴＦＴアレイでは、第５
図、第６図、第７図に示すように、最初の画素電極５形
成時に同時に透明導電膜からなる画素電極材料でゲート
配′！Ｍｌｌを形成し、次いで、ゲート配線１１上にゲ
ート配線１１を覆うように本来のゲート電極及び配ｖＡ
２を形成してゲート配線を２層化する方法が行われてき
た。In general, gate bridges of TFT arrays used in liquid crystal display devices are usually made of high melting point metal such as Cr, which has high heat resistance, but in order to achieve large screens and high resolution, signal attenuation due to wiring resistance is required. In order to prevent delays, etc., it is necessary to increase the film thickness and lower the resistance. However, when the film thickness is increased, the probability of cracks occurring with high-melting point metals such as Cr increases due to film stress.In addition, with higher resolution and larger screens, finer wiring and increased wiring length are required. Therefore, there is a drawback that wire breakage occurs due to defective patterning due to dust, etc., leading to a decrease in yield.To overcome this drawback, in the TFT array of conventional liquid crystal display devices, the fifth
As shown in FIGS. 6, 7, and 7, when the pixel electrode 5 is initially formed, the gate is formed using a pixel electrode material made of a transparent conductive film. Mll is formed, and then the original gate electrode and the wiring are formed on the gate wiring 11 so as to cover the gate wiring 11.
A method has been used in which the gate wiring is formed in two layers by forming the gate wiring.
従来の液晶表示装置は上述のように、ゲート配線を２層
化し、ゲート配線とソース配線の交差部分に画素電極材
料によるゲート配線が存在するように構成しているので
、画素電極材料中のゴミや段差部分等の影響によりゲー
ト配線とソース配線′との短絡が発生し、歩留りの低下
を招くといった問題点があった。As mentioned above, conventional liquid crystal display devices have two layers of gate wiring, and the gate wiring made of pixel electrode material is present at the intersection of the gate wiring and the source wiring, so that dust in the pixel electrode material is removed. There is a problem in that a short circuit occurs between the gate wiring and the source wiring due to the influence of the step portion and the stepped portion, resulting in a decrease in yield.
この発明は上記のような問題点を解消するためになされ
たもので、ソース配線とゲート配線との交差部における
ゲート配線とソース配線との線間短絡欠陥を増加させる
ことなく、ゲート配線の断線欠陥を低減できるＴＦＴア
レイを有する液晶表示装置を提供することを目的とする
。This invention was made in order to solve the above-mentioned problems, and it is possible to eliminate the disconnection of gate wiring without increasing the short-circuit defects between the gate wiring and the source wiring at the intersection of the source wiring and the gate wiring. An object of the present invention is to provide a liquid crystal display device having a TFT array that can reduce defects.
この発明に係る液晶表示装置は、ＴＦＴアレイ基板のゲ
ート電極配線を、ゲート電極配線とソース電極配線との
交差部分を除く部分においては画素電極材料の透明導電
膜と本来のゲート電極配線材料の導体膜の２層構造とし
、かつ、ゲート電極配線とソース電極配線との交差部分
においては導体膜の単層構造としたものである。In the liquid crystal display device according to the present invention, the gate electrode wiring of the TFT array substrate is formed between the transparent conductive film of the pixel electrode material and the original conductor of the gate electrode wiring material in the portion excluding the intersection of the gate electrode wiring and the source electrode wiring. It has a two-layer structure of a film, and a single-layer structure of a conductive film at the intersection of the gate electrode wiring and the source electrode wiring.
この発明の液晶表示装置においては、ゲート配線とソー
ス配線との交差部分以外の部分においてゲート配線が透
明導電膜と導体膜の２層構造となり、また、ゲート配線
とソース配線との交差部分では本来のゲート配線による
導体膜の単層構造となるので、ゲート配線とソース配線
との交差部分でのゲート配線とソース配線との線間短絡
を増加させることなくゲート配線の断線を低減させるこ
とが可能となり、歩留りが向上する。In the liquid crystal display device of the present invention, the gate wiring has a two-layer structure of a transparent conductive film and a conductive film in parts other than the intersections between the gate wiring and the source wiring, and the gate wiring has a two-layer structure of a transparent conductive film and a conductive film in the parts where the gate wiring and the source wiring intersect. Since the gate wiring has a single layer structure of a conductor film, it is possible to reduce disconnection of the gate wiring without increasing line-to-line short circuits between the gate wiring and the source wiring at the intersection of the gate wiring and the source wiring. Therefore, the yield is improved.
以下、本発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例による液晶表示装置のＴＦＴ
アレイの部分平面図、第２図、第３図及び第４図は第１
図のＡ−Ａ’部、Ｂ−Ｂ’部、及びｃ−ｃ’部の断面図
を各々示している。図におで、第５図と同一符号は同一
部分を示し、１１はゲート配線とソース配線との交差部
分以外の部分に画素電極と同時形成したゲート配線であ
る。FIG. 1 shows a TFT of a liquid crystal display device according to an embodiment of the present invention.
Partial plan views of the array, Figures 2, 3 and 4 are
The cross-sectional views of the AA' section, the BB' section, and the c-c' section of the figure are shown, respectively. In the figure, the same reference numerals as in FIG. 5 indicate the same parts, and 11 is a gate line formed at the same time as the pixel electrode in a part other than the intersection of the gate line and the source line.
以下、本実施例の製造方法について説明する。The manufacturing method of this example will be explained below.
まず、ガラス等の透明絶縁基板１上にＩＴＯ（Ｉｎｄｉ
ｕｎ＋ Ｔｉｎ ０ｘｉｄｅ ；酸化インジウムスズ膜
）などの透明導電膜をＥ Ｂ （Ｅｌｅｃｔｒｏｎ Ｂ
ｅａｍ ） ７着法等で堆積する。この後、ホトリソグ
ラフィー等の方法で画素電極５と、ゲート配線２とソー
ス配線３との交差部分のこれより少し幅広の部分を除く
部分にアイランド状のゲート配線１１を形成する。First, ITO (Indi
A transparent conductive film such as un+ Tin Oxide (indium tin oxide film) is coated with E B (Electron B
eam) Deposited using the 7-layer method, etc. Thereafter, an island-shaped gate wiring 11 is formed using a method such as photolithography at the intersection of the pixel electrode 5, the gate wiring 2, and the source wiring 3, except for a slightly wider part.
次にスパッタ等の方法で、Ｃｒ等の金属を堆積し、ゲー
ト電極及びゲート配″！ｌｌＡ２を前記ＩＴＯによるゲ
ート配線１１上にこれより太き（形成する。次にゲー＋
−Ｘ色縁膜６となる５１ｘＮ＜または５ｉＯｚ等、及び
半導体層７となる水素化アモルファスシリコン（ａ−３
ｉ；Ｈ）等を連続してプラズマＣＶＤ法等により全面に
堆積する。次いで、半導体層７をアイランド状に形成し
、ゲート絶縁膜６に画素電極５を接続するためのコンタ
クトホールの形成を行う。次にＡｌなどの金属膜を堆積
し、ソース電極及びソース配線３とドレイン電極４を形
成する。次に、パッシベーション膜８として５ｉｒＮ４
またはＳｉＯ□等を堆積する。そして−括して画素電極
５上のゲート絶縁膜６及びパッシベーション膜８を除去
する。次に半導体層７を形成した部分の上方にへ２等を
堆積して遮光膜９を形成する。Next, a metal such as Cr is deposited by a method such as sputtering, and a gate electrode and a gate wiring 11A2 are formed on the gate wiring 11 made of ITO.
51xN< or 5iOz, etc., which will become the -X color edge film 6, and hydrogenated amorphous silicon (a-3
i; H) etc. are successively deposited on the entire surface by plasma CVD method or the like. Next, the semiconductor layer 7 is formed into an island shape, and a contact hole for connecting the pixel electrode 5 to the gate insulating film 6 is formed. Next, a metal film such as Al is deposited to form a source electrode, source wiring 3, and drain electrode 4. Next, as the passivation film 8, 5irN4
Alternatively, deposit SiO□ or the like. Then, the gate insulating film 6 and passivation film 8 on the pixel electrode 5 are removed all at once. Next, a light-shielding film 9 is formed by depositing a oxide film above the portion where the semiconductor layer 7 is formed.
このようにして形成したＴＦＴアレイ基板と、透明導電
膜及びカラーフィルタ等を有する対向基板との間に液晶
等の表示材料を挟持し、本発明の液晶表示装置を完成す
る。A display material such as liquid crystal is sandwiched between the TFT array substrate thus formed and a counter substrate having a transparent conductive film, a color filter, etc., to complete the liquid crystal display device of the present invention.
上記構成のＴＦＴアレイを備えた液晶表示装置は、ゲー
ト配線２とソース配線３との交差部分以外のすべての部
分において、ゲート配線を２層化しており、しかもパタ
ーニングを別々に行っているため、いずれかの配線にク
ラックあるいはゴミ等によるパターニング不良が発生し
たとしても他方の配線で接続がなされており、断線欠陥
は生じない。しかもゲート配線２とソース配線３との交
差部分は従来のゲート配！ｌ！２の単層構造となってい
るため、ゲート配ｖＡｌｌ上のゴミなどによるゲート電
極配線とソース電極配線との短絡欠陥も生じない。従っ
て、本発明では掻めて表示欠陥の少ない、大面積、高解
像度の液晶表示装置を、高歩留りで得ることができる。In the liquid crystal display device equipped with the TFT array having the above configuration, the gate wiring is formed into two layers in all parts other than the intersection between the gate wiring 2 and the source wiring 3, and patterning is performed separately. Even if a patterning defect due to cracks or dust occurs in one of the wirings, the connection is made through the other wiring, and no disconnection defect occurs. Moreover, the intersection between gate wiring 2 and source wiring 3 is the same as the conventional gate wiring! l! Since it has a single-layer structure as shown in FIG. 2, short-circuit defects between the gate electrode wiring and the source electrode wiring due to dust on the gate wiring vAll do not occur. Therefore, according to the present invention, a large-area, high-resolution liquid crystal display device with fewer display defects can be obtained at a high yield.
なお、上記実施例では半導体層７には水素化アモルファ
スシリコン膜を用いたが、これは多結晶シリコン膜でも
よい。In the above embodiment, a hydrogenated amorphous silicon film is used for the semiconductor layer 7, but a polycrystalline silicon film may be used instead.
また、上記実施例では、ゲート電極配線２の透明導電膜
としてはＣｒを用いたが、これはＣｒの他に、Ｔａ、Ｔ
ｉ、Ｎｉ−Ｃｒ、Ｍｏ、Ａｌ−３ｉ等からなる金属でも
よい。Further, in the above embodiment, Cr was used as the transparent conductive film of the gate electrode wiring 2, but in addition to Cr, Ta, T
It may be made of metal such as i, Ni-Cr, Mo, Al-3i, or the like.
また、上記実施例ではソース電極配線３七ゲート電極配
線２との交差部近傍にはＴＦＴからなる半導体層７を１
つ設けるように構成したが、複数個を並列に設けるよう
に構成してもよい。Further, in the above embodiment, one semiconductor layer 7 made of TFT is placed near the intersection of the source electrode wiring 3 and the gate electrode wiring 2.
Although the configuration is such that one is provided, it is also possible to configure a plurality of such devices to be provided in parallel.
以上のように本発明の液晶表示装置によれば、ゲート配
線とソース配線との交差部分以外の部分にアイランド状
に透明導電膜からなる画電極材料でゲート配線を形成し
、次いで、導体膜により本来のゲート電極及び配線を形
成することにより、ゲート配線とソース配線との交差部
分以外の部分においてはゲート配線を２層構造、また、
ゲート配線とソース配線との交差部分においてはゲート
配線を単層構造としたので、ゲート配線とソース配線と
の交差部分の線間短絡を防止でき、しかも、ゲート配線
の断線を低減でき、高歩留りを実現できる効果がある。As described above, according to the liquid crystal display device of the present invention, the gate wiring is formed in an island shape using a picture electrode material made of a transparent conductive film at a portion other than the intersection of the gate wiring and the source wiring, and then the gate wiring is formed using a picture electrode material made of a transparent conductive film. By forming the original gate electrode and wiring, the gate wiring can be formed into a two-layer structure in areas other than the intersections between the gate wiring and the source wiring, and
Since the gate wiring has a single-layer structure at the intersection between the gate wiring and the source wiring, it is possible to prevent short circuits between the lines at the intersection between the gate wiring and the source wiring, and also to reduce disconnection of the gate wiring, resulting in a high yield. It has the effect of realizing
第１図は本発明の一実施例による液晶表示装置のＴＦＴ
アレイの部分平面図、第２図は第１図のＡ−Ａ’部の断
面図、第３図は第１図のＢ−Ｂ“部の断面図、第４図は
第１図のｃ−ｃ’ 部の断面図、第５図は従来の液晶表
示装置のＴＦＴアレイの部分平面図、第６図は第５図の
Ｄ−Ｄ’ 部の断面図、第７図は第５図のＥ−Ｅ’部の
断面図である。
１は透明絶縁性基板、２はゲート電極及び配線、３はソ
ース電極及び配線、４はドレイン電極、５は画素電極、
６はゲート絶縁膜、７は半導体層、８はパッシベーショ
ン膜、９は想光膜、１０はドレイン電極と画素電極との
コンタクト部分、１１は画素電極と同時形成したゲート
配線である。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 shows a TFT of a liquid crystal display device according to an embodiment of the present invention.
A partial plan view of the array, FIG. 2 is a sectional view taken along line AA' in FIG. 1, FIG. 3 is a sectional view taken along line BB'' in FIG. 5 is a partial plan view of a TFT array of a conventional liquid crystal display device, FIG. 6 is a sectional view of section DD' in FIG. 5, and FIG. 7 is a sectional view taken along line E in FIG. 5. - It is a sectional view of the E' part. 1 is a transparent insulating substrate, 2 is a gate electrode and wiring, 3 is a source electrode and wiring, 4 is a drain electrode, 5 is a pixel electrode,
6 is a gate insulating film, 7 is a semiconductor layer, 8 is a passivation film, 9 is a photoreceptor film, 10 is a contact portion between the drain electrode and the pixel electrode, and 11 is a gate wiring formed at the same time as the pixel electrode. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
ース電極配線と、 上記ゲート電極配線とソース電極配線との交差部の近傍
に配置された、少なくとも１個の非線型特性を持つ薄膜
トランジスタ（以下、ＴＦＴと略す）と、 該ＴＦＴのドレイン電極に接続された透明導電膜である
表示電極とを備えてなるＴＦＴアレイ基板を有するとと
もに、 透明導電膜を有する対向電極基板と、 上記ＴＦＴアレイ基板と対向電極基板との間に挟持され
た液晶材料とを有する液晶表示装置において、 上記ＴＦＴアレイ基板のゲート電極配線は、該ゲート電
極配線と上記ソース電極配線との交差部分を除く部分に
おいては上記透明導電膜と導体膜の２層構造とし、かつ
上記ゲート電極配線とソース電極配線との交差部分にお
いては導体膜の単層構造としたことを特徴とする液晶表
示装置。(1) On a transparent insulating substrate, a plurality of gate electrode wirings, a plurality of source electrode wirings formed to intersect with the gate electrode wirings, and a vicinity of the intersection of the gate electrode wirings and the source electrode wirings. A TFT array substrate comprising at least one thin film transistor (hereinafter abbreviated as TFT) having non-linear characteristics arranged in the TFT, and a display electrode which is a transparent conductive film connected to the drain electrode of the TFT. In addition, in a liquid crystal display device having a counter electrode substrate having a transparent conductive film, and a liquid crystal material sandwiched between the TFT array substrate and the counter electrode substrate, the gate electrode wiring of the TFT array substrate is connected to the gate electrode. The portions excluding the intersections between the wiring and the source electrode wiring have a two-layer structure of the transparent conductive film and the conductor film, and the intersections between the gate electrode wiring and the source electrode wiring have a single-layer structure of the conductor film. A liquid crystal display device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5340188A JP2695424B2 (en) | 1988-03-07 | 1988-03-07 | Liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5340188A JP2695424B2 (en) | 1988-03-07 | 1988-03-07 | Liquid crystal display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01227128A true JPH01227128A (en) | 1989-09-11 |
| JP2695424B2 JP2695424B2 (en) | 1997-12-24 |
Family
ID=12941806
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5340188A Expired - Fee Related JP2695424B2 (en) | 1988-03-07 | 1988-03-07 | Liquid crystal display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2695424B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02184824A (en) * | 1989-01-10 | 1990-07-19 | Fujitsu Ltd | Thin-film transistor matrix |
| JPH03118520A (en) * | 1989-09-29 | 1991-05-21 | Sharp Corp | Thin film transistor array |
| JPH04186233A (en) * | 1990-11-21 | 1992-07-03 | Toshiba Corp | Matrix array substrate |
| JP2012191008A (en) * | 2011-03-10 | 2012-10-04 | Sony Corp | Display device and electronic apparatus |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61105582A (en) * | 1984-10-29 | 1986-05-23 | 富士通株式会社 | Manufacture of thin film transistor matrix |
| JPS6265468A (en) * | 1985-09-18 | 1987-03-24 | Toshiba Corp | Display device |
| JPS62205390A (en) * | 1986-03-06 | 1987-09-09 | 株式会社東芝 | Substrate for display unit |
| JPS62288882A (en) * | 1986-06-09 | 1987-12-15 | アルプス電気株式会社 | Manufacture of thin film transistor |
| JPS639977A (en) * | 1986-07-01 | 1988-01-16 | Citizen Watch Co Ltd | thin film transistor |
-
1988
- 1988-03-07 JP JP5340188A patent/JP2695424B2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61105582A (en) * | 1984-10-29 | 1986-05-23 | 富士通株式会社 | Manufacture of thin film transistor matrix |
| JPS6265468A (en) * | 1985-09-18 | 1987-03-24 | Toshiba Corp | Display device |
| JPS62205390A (en) * | 1986-03-06 | 1987-09-09 | 株式会社東芝 | Substrate for display unit |
| JPS62288882A (en) * | 1986-06-09 | 1987-12-15 | アルプス電気株式会社 | Manufacture of thin film transistor |
| JPS639977A (en) * | 1986-07-01 | 1988-01-16 | Citizen Watch Co Ltd | thin film transistor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02184824A (en) * | 1989-01-10 | 1990-07-19 | Fujitsu Ltd | Thin-film transistor matrix |
| JPH03118520A (en) * | 1989-09-29 | 1991-05-21 | Sharp Corp | Thin film transistor array |
| JPH04186233A (en) * | 1990-11-21 | 1992-07-03 | Toshiba Corp | Matrix array substrate |
| JP2012191008A (en) * | 2011-03-10 | 2012-10-04 | Sony Corp | Display device and electronic apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2695424B2 (en) | 1997-12-24 |
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