JPH01229342A - Microprocessor runaway check device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an apparatus using a microprocessor.
The present invention relates to a microprocessor runaway check device that checks runaway of the microprocessor itself.

[Prior Art J] Conventionally, some devices using microprocessors (hereinafter referred to as CPUs) have the function of detecting and diagnosing abnormal conditions in peripheral devices controlled by the CPU. When the CPU goes out of control due to a fetch error or a software bug, it is not possible for the CPU itself to recognize the runaway state.

1. Problems to be Solved by the Invention] It is generally known that when a CPU goes out of control, it accesses all areas of memory. Therefore, if the CPU goes out of control, the data area will be destroyed and all important information will be lost.

Since it is basically impossible to recover the information, it is necessary to restart all settings and registration from the beginning. This is a tedious task and may be redundant for some users. Furthermore, some registered contents cannot be redone.

Furthermore, even if it is determined that the CPU has runaway, it is not easy to investigate and eliminate the cause of the runaway.

In view of these conventional problems, it is an object of the present invention to provide a microprocessor runaway check device that protects the data area from CPU runaway and at the same time allows for easy investigation and removal of the cause of runaway. It is about providing.

[Means for solving the problem] In the invention described in item 1, in an apparatus having a microprocessor, a program memory storing a program, and a data memory storing data, a check memory and a data area of the data memory are provided. A detection circuit detects that one of a plurality of specific addresses that are specified not to be accessed during normal program operation is accessed by the microprocessor and outputs an interrupt signal to the microprocessor; a write control circuit that selects the operation of the microprocessor to enable writing to the check memory on the condition that an interrupt signal is not output, and prohibits writing to the check memory on the condition that an interrupt signal is output; The present invention is characterized by comprising means for causing a microprocessor to execute a predetermined process based on an interrupt signal from the detection circuit, and for causing a display indicating that a runaway has occurred.

In the invention described in item 2, in the device having a microprocessor, a program memory storing a program, and a data memory storing data, the microprocessor detects that a write signal is output to the check memory and the program memory, and the microprocessor a detection circuit that outputs an interrupt signal to the check memory; and a detection circuit that selects the operation of the microprocessor so that it can write to the check memory on the condition that no interrupt signal is output from the detection circuit, and detects that the interrupt signal is output. a write control circuit that prohibits writing into the check memory as a condition; and means for causing the microprocessor to execute predetermined processing based on the interrupt signal from the detection circuit and displaying that there has been a runaway. It is characterized by having the following.

[Function] In the invention described in item 1, when the microprocessor goes out of control, the microprocessor accesses one of the specific addresses in the data memory, so the detection circuit outputs an interrupt signal to the microprocessor and also performs a check. Writing to memory is prohibited. Then, the microprocessor executes predetermined interrupt processing, so the data in the data memory is not destroyed.
Since the operation of the microprocessor up to the time when the runaway of the microprocessor is detected by the detection circuit is stored in the check memory, the cause of the runaway can be easily investigated and removed by reading the contents of the check memory.

In the invention described in item 2, when a write signal is issued to the program memory due to a runaway of the microprocessor, an interrupt signal is output from the detection circuit to the microprocessor, and writing to the check memory is prohibited. Therefore, like the invention described in item 1, the data in the data memory is not destroyed, and the cause of runaway can be easily investigated and removed.

[Example code] Embodiments of the present invention will be described below based on the drawings.

The first embodiment is shown in FIGS. 1 to 4, and in FIG. 2,
The microprocessor (CPU) 11 includes a program memory 13 storing programs, a data memory 14 storing data, a CPU runaway check circuit 15, a keyboard 16, and a display via an address/data bus, a control signal line 12, etc. 17 are connected to each other.

The CPUJ% running check circuit 15, as shown in FIG.
detecting that any one of a plurality of specific addresses, which are defined in advance not to be accessed during normal program operation, has been accessed by the CPU II among the check memory 21 that stores the movement of the CPU and the data area of the data memory 14; A detection circuit 31 outputs the interrupt signal NMI to the CPU II, and the operation of the CPU 11 is selected to be writeable to the check memory 21 on the condition that the interrupt signal NMI is not output from the detection circuit 31. It also includes a write control circuit 41 that prohibits writing to the check memory 21 on the condition that the check memory 21 is output.

Check memory 21 is connected to the CPU II via address bus 12A and data bus 12D. The detection circuit 31 includes AND gates AGI, AG2 . AG
5. It is configured to include AC3, inverter IN2, and flip-flops FFI and FF2. Write control circuit 4
1 is AND gate AG3. AG4, Or Gate OG
It is configured to include I, OG2, and inverter INI.

When the I10 address C3I is written <CSt, IOW are both at the “L” level), the AND gate AG1 becomes “L”.
” level output is given to the R (reset) terminal of flip-flop FFI. The output from the AND gate AG2 is given to the S (set) terminal of the flip-flop FFI. AND gate AG2 is I10 address C8
When O is written (CSOLIOW and both are at "L" level), an "L" level signal is output.

The output from the Q output terminal of flip-flop FFI is connected to one input terminal of AND gate AG3, inverter INI.
After being inverted via the input gate AG4, the signal is input to one input terminal of the AND gate AG4 and the R (reset) terminal of the flip-flop FF2. The read signal MR from the CPU 11 is connected to the other input terminal of the AND gate AG3, and the check memory 2 is connected to its output terminal.
1 output enable terminal OE is connected. The read signal port is connected to the other input terminal of AND gate AG4, and one input terminal of OR gate OG2 is connected to its output terminal.

The other input n1 child of OR gate OG2 has CPU II.
The write enable terminal WE of the check memory 21 is connected to its output terminal. The output of the OR gate OGI is input to the chip select terminal C8 of the check memory 21. The output of the inverter INI and the address chip select signal MSCO from the CPU 11 are respectively input to the OR gate OGI. Further, the output from the OR gate oG2 is inverted by an inverter IN2 and then input to the T input terminal of the flip-flop FF2.

In the reset state, the flip-flop FF2 is D
When the output from the AND gate AG5 input to the input terminal is at the rH level, and the 'r input terminal is at the rH level, an interrupt signal NMI causes the interrupt process shown in FIG. 4 to be executed. Output. AND gate AG5 has the output of AND gate AG6 and memory select signal IO.
/M is input respectively. The AND gate AG6 receives the data area select signal and a specific address of the data area of the data memory 14 that is specified not to be accessed in advance during normal program operation, in this case, when the addresses A7 to AO go to the "H" level. Outputs an L level signal.

Next, the operation of this embodiment will be explained with reference to FIGS. 3 and 4.

Now write I10 address C3I (C3I, IOW
, both at "L" level), Flip Flora 1FF
Since I is reset, Q of flip-flop FFI
An "L" level signal is output from the output terminal. For this reason, flip-flop FF2 is reset, so
The interrupt signal NMI is not output. At this time, the AND gate AG4 is closed and the AND gate AG3 is opened, so that the CPU II can normally write/read the check memory 21.

Now, to start the CPU runaway check circuit 15, as shown in FIG. 3, write the I10 address CSO (both C3O1IOW are set to "L" level). Then,
From the Q output terminal of the flip-flop r"F1, r
A signal of H level is output. Due to this, the flip roller 1FF2 is brought into a reset release state. At this time,
Ant game-1' Ac1 is closed, and gate A
G4 will be held.

Also, r from the Q output terminal of flip-flop FFI
After the signal at level I-1 is inverted by the inverter INI, it is input to the chip select terminal C8 of the check memory 21 through the OR gate OGI, that is, the chip select terminal C8 is always at the "L" level.
And read/write signals MR, MW are OR gate O
Since it is input to the write enable terminal WE of the check memory 21 through G2, when the CPU II accesses the program memory 13 and the data memory 14, all the operations are written to the check memory 21.

By the way, it is known that when the CPU II goes out of control, the CPU 11 accesses all areas of the memory 13 and 14. Now, when the CPU II goes out of control, it accesses any of the specific addresses (A7 to AO) of the data memory 14. Then, the data area select signal and addresses A7 to AO both reach the level r)f.
The output of AND gate AG6 becomes "L" level. Here, when the memory select signal IO/M goes to the "yes" level, the output of the AND gate AG5 goes to the rH level and is applied to the D output terminal of the flip-flop FF2.

At this time, when read signal n or write signal MW is input, those signals are inverted by inverter IN2 and then input to the T input terminal of flip-flop FF2, so that the Q output terminal of flip-flop FF2 is rH ，
A level interrupt signal NMI is output to the CPU II.

Then, the CPU II proceeds to the interrupt processing shown in the flowchart of FIG. 4, and escapes from the runaway state.

Therefore, since the CPU II will no longer access the memory, the data in the data memory 14 can be retained. In FIG. 4, first, the I10 address ξSl is written. Then, in the same manner as described above, the flip-flop FFL is reset and the output from the Q output terminal of the flip-flop FFI goes to "L" level, so the flip-flop 1FF2 is reset and the interrupt signal NMI is disabled. , the chip select terminal C8 of the check memory 21 becomes the "I" level via the inverter INI and the OR gate OGI, and writing to the check memory 21 is prohibited.

Subsequently, after displaying a comment to the effect of the runaway on the display 17, the keyboard 16 gives a command to continue reading the check memory 21.Here, when the command to continue reading the check memory 21 is given from the keyboard 16, the contents of the check memory 21 are read out. It is displayed on the display 17.

As a result, the user can see the content displayed on the display 17,
In other words, by looking at the circumstances leading up to the CPU II running out of control, we investigate and eliminate the cause of the runaway.

Therefore, according to this embodiment, the operation of the CPU II is stored in the check memory 21, and when a specific address of the CPU 11 or the data memory 14 is accessed, that is, when a runaway occurs, the CPU is In addition to operating within the CPU II, writing to the check memory 21 is prohibited, so even if the CPU II goes out of control, the CPU
Only the area up to the first specific address in data memory 14 accessed by II can be destroyed.

In addition, CPU1l until it is detected that the CPU11 is running out of control.
The operation is stored in the check memory 21, so by reading the contents of the check memory 21, it is possible to investigate the cause of the runaway.
It can also be easily removed.

In addition, when CPU II runaway is detected, the display 1
5, so that the user can recognize that the CPU II is running out of control from this display. Therefore, immediate action can be taken.

The second embodiment is shown in FIG.
Components that are the same as those in the embodiment are given the same reference numerals, and the explanation thereof will be omitted or simplified.

This embodiment is similar to the first embodiment except that it includes a detection circuit 31A that detects the arrival of a write signal to the program memory 13 and outputs an interrupt signal NMI to the CPU II that causes the interrupt processing shown in FIG. 4 to be executed. Same as example. Therefore, the write signal NIW is input to the 'r input terminal of the flip-flop 1FF2 of the detection circuit 31A via the inverter IN3.

Further, a program select signal is input to the D input terminal of the flip-flop 1FF2 via an inverter IN4.

Therefore, when the CPU II goes out of control and a write signal MW is output to the program memory 13, a signal of rH level is input to the D input terminal of the flip-flop FF2 via the inverter IN4, and a signal of level rH is input to the T input terminal of the flip-flop FF2. Since the "H" level signal is input, the rH level interrupt signal NMI is output from the Q output terminal of the flip-flop 1FF2. This allows the CPU
II is operated according to the flowchart in FIG.

Therefore, even in this embodiment, the same effects as in the first repair example can be achieved.

Note that in the above embodiment, in the interrupt processing shown in FIG.
Although the display unit 17 displays the fact that there has been a runaway, it may also be displayed by a printer or the like.In other words, the display that there has been a runaway is
It is not limited to a display, but any means that can communicate to people may be used.

[Effects of the Invention] As described above, according to the present invention, when a specific address of the data memory is accessed or a write signal is output to the program memory, the detection circuit detects these and sends the information to the microprocessor. This protects the data in the data memory by outputting an interrupt signal, causing the microprocessor to execute a predetermined interrupt process, displaying an indication that a runaway has occurred, and prohibiting writing to the check memory. can do. Furthermore, since the microprocessor's operations until the detection circuit detects the runaway of the microprocessor are stored in the check memory, the cause of the runaway can be easily investigated and removed by reading the contents of the check memory. can.

[Brief explanation of the drawing]

1 to 4 show a first embodiment of the present invention, in which FIG. 1 is a circuit diagram showing a cpua=t check circuit, FIG. 2 is a block diagram showing a device using a CPU, and FIG. 3 is a block diagram showing a device using a CPU. 4 and 4 are flowcharts, respectively. FIG. 5 is a circuit diagram showing a CPU runaway check circuit according to a second embodiment of the present invention. 11...CPU, 13...Program memory, 14
...Data memory, 15...CPUJ & running check circuit, 21...Check memory, 31, 31A...
Detection circuit, 41...Write control circuit.

Claims (2)

[Claims] (1) In a device having a microprocessor, a program memory for storing programs, and a data memory for storing data, a check memory and a plurality of specified data areas of the data memory that are specified not to be accessed during normal program operation are provided. a detection circuit that detects that any of the addresses has been accessed by the microprocessor and outputs an interrupt signal to the microprocessor; a write control circuit that selects to enable writing to the check memory and prohibits writing to the check memory on condition that an interrupt signal is output; 1. A microprocessor runaway check device, comprising means for executing a process and displaying a message indicating that a runaway has occurred. (2) In a device having a microprocessor, a program memory for storing programs, and a data memory for storing data, detecting that a write signal is output to the check memory and the program memory, and sending an interrupt signal to the microprocessor. Select a detection circuit to output, and write the operation of the microprocessor to the check memory on the condition that no interrupt signal is output from this detection circuit, and write the operation of the microprocessor to the check memory on the condition that the interrupt signal is output. and a means for causing a microprocessor to execute a predetermined process based on an interrupt signal from the detection circuit and displaying an indication that a runaway has occurred. Features a microprocessor runaway check device.