JPH01231126A - Information processor - Google Patents

Abstract

PURPOSE:To decrease the waiting time by using the write data concerned instead of read-out data of the instruction concerned, when a write address of a preceding instruction and a read-out address of the instruction concerned coincide, at the time of executing a pipeline processing. CONSTITUTION:In an I stage, an instruction reading-out circuit 2 reads out an instruction to an instruction register 6 of an arithmetic circuit 1 from a cache memory 4 or a main storage device 5. In an R stage, by a rise of a clock passing through an AND gate AND, each instruction OP, D, S0 and S1 is set to the instruction register 6, and by register read-out addresses S0, S1, the contents of a register file 12 are read out to buses L0, L1. Simultaneously, addresses S0, S1 are set to a register interference detecting circuit 8, an instruction code OP is set to an instruction decoder 7, and a result of decoding by the instruction decoder 7 is set to the register interference detecting circuit 8. If an interference is generated, read-out of the instruction register is stopped, and unless the interference exists, if the preceding write address and the read-out address concerned coincide, write data is used as read-out data.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information processing device, and particularly to a register interference control circuit in pipeline control.

(Prior Art) Conventionally, in a pipeline-controlled information processing device that processes a plurality of instructions in parallel,
As described in Publication No. 5, an instruction to read a register file and perform various processing, such as an addition instruction (hereinafter referred to as A
instruction), immediate value addition instruction (hereinafter referred to as AI instruction)
When executing arithmetic instructions such as , comparison instructions (hereinafter referred to as C instructions), the contents of the register file specified for reading in each instruction are changed from the preceding instruction, such as a load instruction (hereinafter referred to as an L instruction). When the contents of the register file are changed by executing an instruction that stores data in the register file, such as when the preceding instruction changes the register file, the corresponding operation is executed after the preceding instruction changes the register file. The command is executed.

Fig. 2 is a diagram showing an example of an arithmetic instruction according to the present invention, Fig. 3 is a time chart in which the instruction shown in Fig. 2 is executed without register interference, and Fig. 4 is a diagram showing the completion of the preceding instruction due to register interference. It is a time chart when waiting.

In FIG. 2, OP is an instruction code, D is a register file write address, SO and SL are register file read addresses, and ■ is immediate data. Each instruction shown in FIG. 2 is an I, R, E
Vibration line control is performed as shown in Fig. 3 using five stages: , P, and W. The stage reads instructions, and the R stage reads register files and decodes instructions.
Immediate data generation by AI or L instructions, addition by A or AI instructions, address calculation by L instructions, and comparison by C instructions in the E stage, data access by L instructions in the P stage In the W stage, register writing is executed using the A instruction, the AI instruction, and the L instruction.

In FIG. 4, if instruction 1 is an L instruction and instruction 2 is, for example, an A instruction, the L instruction calculates an address in the E stage and stores the data read from the cache, main memory, etc. in the P stage. , A wait state indicated by X occurs due to register interference between register reading in the R stage and addition in the E stage by the A instruction.

This type of register interference is achieved by extracting bits from the instruction that indicate the read address of the register file and the write address of the preceding instruction, and using a comparison circuit to determine if these two addresses match. detected if

(Problem to be Solved by the Invention) However, in the method of detecting register interference as described above, even if the preceding instruction is an instruction that does not write to the register file, or the instruction to be executed does not read the register file, Even if the bits indicating the address are extracted from the instruction, the register interference will be detected by the comparator.

As described above, register interference is detected even when no register interference should occur, resulting in an unnecessary waiting time until the preceding instruction is completed, resulting in a reduction in processing performance.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide an information processing device in which no waiting time occurs when register interference is not occurring.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a stage for reading an instruction signal from an instruction register, and a stage for reading data for operation from a register file based on the instruction signal. In an information processing device that performs pipeline control and has a stage for performing an operation using the operation data by an arithmetic unit and a stage for writing the operation result to a register file, an address for writing to the register file by a preceding instruction is provided. address holding means that holds the address for each stage, and compares the read address of the register file by the instruction with the write address of each stage held in the address holding means and outputs a mutual match signal or mismatch signal. register interference setting means for setting whether register interference occurs for each stage between each stage of the preceding instruction held by the address holding means and the stage of the current instruction; an instruction stopping means for stopping reading of the instruction register at a stage where the register interference occurs; and when the comparing means outputs a match signal at a stage at which the register interference does not occur, the data of the stage according to the preceding instruction is transferred to the register according to the current instruction. and gate means for supplying the data to the arithmetic unit in place of the read data of the file.

(Function) According to the present invention, if register interference occurs between the write address of each stage by the preceding instruction and the stage by the instruction, reading of the instruction register is stopped, and if register interference does not occur, reading of the instruction register is stopped. For example, if the write address of the preceding instruction and the read address of that instruction match, then instead of the data read from the register file by the current instruction, the data of that stage by the preceding instruction is given to the arithmetic unit, and the process continues. each stage is executed.

(Embodiment) FIG. 5 is a block diagram showing the main part configuration of an information processing device as an embodiment of the present invention, in which 1 is an arithmetic circuit, 2 is an instruction reading circuit, 3 is a data access circuit, and 4 is a cache memory. , 5 is the main storage device.

FIG. 1 is a block diagram showing the configuration of the arithmetic circuit 1 shown in FIG.
FIG. 6 is a block diagram showing the configuration of the register interference detection circuit 8 of FIG. 1.

In FIG. 1, 6 is an instruction register that stores the arithmetic instruction shown in FIG. 1, AND is an AND gate as an instruction stopping means, and 7 is an instruction decoder that decodes the instruction code OP.
8 is a register interference detection circuit for detecting register interference between each stage of the preceding instruction and the stage of the instruction; 9;
10.11 are each stage E, P, W of the preceding instruction, respectively.
12 is a register file, 13 is a register that stores read data (SO) of the register file 12, etc., and 14 is a register that stores read data (Sl) of the register file 12 and an instruction register. 6 is a register for storing immediate value data I, etc.; 15 is a register for storing each of these data (So), (Sl
), a computing unit that performs four arithmetic operations on I, 16 is eL
A register that stores the output data of the calculator 15, 17 a switching circuit that switches between the data in the register 16 and read data by the data access circuit 3, 18 a register that stores the data via the switching circuit 17, and 01 to GB, Each gate serves as gate means for bypassing data from the register 18, switching circuit 17, arithmetic unit 15, etc. to bus LO or Ll.

In FIG. 6, 19 to 24 are each read address SO or SL according to the instruction, and each register 9, 10, 11.
25, 26, and 27 are signals decoded by the instruction decoder 7, which will be described later, in synchronization with the registers 9, 10, and 11. Flag register that stores d1゜d2, M1
~M6 is a logic circuit as a register interference setting means that sets whether or not register interference occurs at each stage for each instruction type, and Me is a logic circuit that generates an activation signal ge for the AND gate in FIG. be.

Next, the operation of the information processing apparatus shown in FIGS. 5 and 1 will be explained using the A instruction shown in FIG. 2 as an example.

Referring to FIG. 3, in stage (2), the instruction reading circuit 2 reads an instruction from the cache memory 4 or the main storage device 5 to the instruction register 6 of the arithmetic circuit 1.

In the R stage, at the rising edge of the clock CLOCK via the AND gate AND, each instruction OP,
Set D, So, St, register read address S
The contents of the register file 12 (So
), (SL) to bus LO.

Read to Ll. At the same time, addresses SO and St are set in the register interference detection circuit 8, the instruction code OP is set in the instruction decoder 7, and the result of decoding by the instruction decoder 7 is set in the register interference detection circuit 8.

At the E stage, the contents (SO) and (SL) of the register file read to buses LO and Ll are set in registers 13 and 14, and the arithmetic unit 15 adds them (SO) +
Execute (SL'). Then, register 9 sets write address D. In the P stage, the arithmetic unit 15
The output (SO) + (SL) of is set in the register 16, and the calculation result (
Set So ) + (SL). register 10
sets the contents of register 9 (write address D). In the W stage, the contents of the register 10 (write address D) are set and output as the write address D to the register file 12, and the operation result (sO) + (SL
) is written from the register 18 to the register file 12.

Next, in the C instruction, the operation is the same as the A instruction in the ■ stage and the R stage, but in the E stage, after the comparison operation (S 0) - (Sl) is executed in the arithmetic unit 15, the P stage and W stage In this case, nothing happens and writing to the register file 12 is not executed.

Next, in the AI instruction, the immediate address ■ of the instruction register 6 is set to the bus Ll in the R stage. The rest is an addition operation (So)+1 similar to the A instruction.

Next, in the L instruction, the operation (So) + I is the same as the AI instruction up to the E stage, and in the P stage, the output (So) + 1 of the arithmetic unit 15 is used as the address, and the address is passed through the register 16 and the data access circuit 3 to the cache memory 4. Or access the main storage device 5 and read the data ((So)+I)
is set in the register 18 via the switching circuit 17.

At the W stage, the write address D of register 11 and the read data of register 18 ((SO>+1
) is written to the register file 12.

Next, the register interference detection circuit 8 shown in FIG. 6 will be explained.

The signal dl of the instruction decoder 7 is used to read the register after waiting for the completion of the preceding instruction when register interference is detected, which will be described later.
In other words, it becomes “1” with the L command, A command, AI command, C
Set to “0” by command. The signal d2 becomes "1°" when the register write address D is valid, that is, for the life support, AI command, and L command, and becomes "0" for the C command.The signal d3 is
When the register read address SO is valid, that is, A, AI
.

When the register read address St is valid, that is, when the register read address St is valid, that is, when the A and C instructions are used, the signal d4 is 1°.
becomes "0" with L command and AI command.Signal line ro
, rl respectively contain the register read address S in the instruction.
O and register read address S1 or immediate address I
and signal lines De, Dp, and Dv have E and P, respectively.
, the register write address D of the instruction executing the W stage (hereinafter, these will be designated as the write address De as appropriate).

Dp, Dv) are received from each register 9.10.11. Comparators 19.20, 21, 22°23.24 compare these read addresses SO, St with write addresses De, Dp, Dv in each stage E, P, W, and output "1m" when they match. Flag register 25
, 26 and 27 sequentially set the signals di and d2 in synchronization with the write address D(3, Dp, Dv).

Now, paying attention to the comparator 19, the read address SO and the write address De match, the signal d3 is 1'', and the signal d2 is
If the signal dle is "0" when e is "1", the signal g5 is set to "1" via the logic circuit Ml to detect the absence of register interference, and if the signal die is 111, the logic circuit Me
Register interference is detected by setting the signal ge to mO'' through register interference is detected when the write address De is valid (d2e is "1") and each read address SO and write address De match.

When the signal ge becomes “0°,” referring to FIG. 4, the access data ((So)+1
) is connected to register 1 via access circuit 3 and switching circuit 17.
Until it is set to 8, the setting to the instruction register 6 is stopped by the gate AND, and reading of the register 6 by, for example, the A instruction is made to wait in the instruction 2 as in the X state in FIG.

Next, see FIGS. 3 and 4 for the case where instruction 1 is A or AI instruction (d le is "0"), comparator 19 is "1", and signal g5 is "1". and explain.

For example, if instruction 1 is an A instruction and instruction 2 is an AI instruction, and the write address D of instruction 1 and the read address SO of instruction 2 specify the same address in the register file 12, as mentioned earlier, the E stage of instruction 1 (Machine cycle-3)
, the arithmetic unit 15 executes addition, and the result is written to the register file 12 at the W stage (machine cycle -5) of instruction 1. If instruction 2 were to read the written contents from the register file 12 and execute the operation, the R stage of instruction 2 would have to wait until after machine cycle 5 to read the register file and then execute the operation. X as shown in Figure 4
However, if the signal g5 is "1" in FIG. 1, the gate G5 is opened, and the result of the operation of the arithmetic unit 15 is transferred through the register G5 at the E stage of the instruction 1. Set in register 13. The contents set in register 13 are the same as those written to register file 12 in machine cycle 5, and in the R stage of instruction 2, the contents of instruction 2 are written without reading the contents of register file 12 specified by SO. At E stage, register 13 and register 14 (value specified by I of AI instruction by instruction 2)
is calculated by the arithmetic unit 15 according to the contents of (machine cycle 4), and the result is written to the register file 12 in machine cycle 6. Therefore, as shown in FIG. 3, instructions can be executed without the need for an X state.

(Effects of the Invention) As explained above, according to the present invention, in a stage where register interference does not occur, when the write address of the preceding instruction and the read address of the instruction match, data at the write address of the preceding instruction is read. By using it in place of the read data of the command, the wait state of the vibe line for the read operation by the command is no longer necessary, so that the processing capacity of the information processing device can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an arithmetic circuit of an information processing device according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of an arithmetic instruction, and FIG. 3 is a time chart during execution of an arithmetic instruction on the vibe line. , FIG. 4 is a time chart when waiting for the end of the execution of the preceding instruction on the vibe line, and FIG. 5 is a block diagram showing the main part configuration of an information processing device including the arithmetic circuit of FIG. 1.
FIG. 6 is a block diagram showing the configuration of the register interference detection circuit shown in FIG. 1. 6...Instruction register, 7...Instruction decoder, 8...
Register interference detection circuit 1.9.10.11...Register (address holding means), 12...Register file, 15...Arithmetic unit, 19,20,21,22,23゜24...Comparison instrument (comparison means), Ml, M2. M3゜M
4, M5, M6, Mc... logic circuit (register interference setting means), Gl, G2. G3. G4. G5゜G6
...gate (gate means), AND...and gate (instruction stop means). Patent Applicant Oki Electric Industry Co., Ltd. Agent Patent Attorney Yoshi 1) Sei Takashi Ayo 4 m2nini [Konicho■! [] ≦ Giant = [I [2■2333333] (So) + (S+) - DC bone "[]
Yo] ['■ Yoyo (So) - (S+) Al analysis - [Work ■ Σ mouth]] (So) + I-DL Command [Hit the ball to Koni = 2 I
EΣ2IHI ■■2=]■Nininini=] New year's entry-,
,45x7 Tray 1 Figure 3

Claims (1)

[Claims] A stage for reading an instruction signal from an instruction register, a stage for reading data for operation from a register file based on the instruction signal, and a stage for performing an operation by an arithmetic unit using the data for operation. An information processing device that performs pipeline control and has a stage for writing the operation result to a register file, the information processing device comprising: an address holding means for holding at each stage an address to be written to the register file by a preceding instruction; Comparing means for comparing the read address of the register file and the write address of each stage held in the address holding means and outputting a mutual match signal or mismatch signal; register interference setting means for setting whether or not register interference occurs for each stage of the instruction and the stage of the current instruction; and an instruction for stopping reading of the instruction register at the stage where the register interference occurs. a stopping means; and a gate means for supplying data of the stage according to the preceding instruction to the arithmetic unit in place of read data of the register file according to the current instruction when the comparing means outputs a match signal at a stage where the register interference does not occur. An information processing device comprising: