JPH01231128A - Fault processing system - Google Patents

Abstract

PURPOSE:To quickly eliminate an intermittent fault by executing a retry in case there is no response for a prescribed time against an output of an access request to a memory device from a data processor and executing a fault processing when the number of times of the retry has reaches a prescribed number of times. CONSTITUTION:A memory request address and a request factor from a microprogram control part 10 of a data processor 1 are supplied to a system controller 2. Subsequently, monitor timer 17 is started and count-up is started. When a reply signal is returned, it is inputted to the microprogram control part 10, and also, inputted as a reset signal to the monitor timer 17. However, when there is no reply signal and a prescribed time elapses, the monitor timer 17 detects time-out and outputs a logical value '1' to a retry counter 18 and a fault flip-flop 21, and starts a retry.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a failure handling method, and more particularly to failure handling when no response is returned to a memory request from a data processing device controlled by a microprogram to a memory device.

Conventionally, this type of data processing apparatus has had a stall monitoring timer that monitors the processing time of each microprogram processing unit. Therefore, if a failure occurs in which the data processing device does not return a response to memory request processing, the stall monitoring timer times out and the failure is detected.
IIi damage was judged to be a serious failure and was treated as a device failure.

In such conventional data processing equipment, if a failure occurs in which no response is returned to memory request processing, this failure is detected by a stall monitoring timer, the failure is determined to be a serious failure, and the equipment is shut down. Since it was treated as a failure, there is a high probability that the system will go down.

In addition, as the scale of equipment has increased in recent years, the failure rate of large systems has increased, the number of channels per equipment has increased, and the usage rate of microprogram control units has increased due to the adoption of new architectures. ,
The number of memory requests in microprogram control units continues to increase.

As a result, failures such as no response to memory request processing increase, and even if the failure is an intermittent failure, the failure is detected by the stall monitoring timer and becomes a device failure, increasing the probability of system failure. It has the disadvantage of becoming.

The present invention has been made in order to eliminate the drawbacks of the conventional devices as described above, and is capable of preventing device failures in the event of intermittent failures and allowing normal operation to continue. The purpose is to provide a processing method.

Further, the failure handling method according to the present invention is a failure handling method for a data processing device that receives a response signal from a memory device in response to an access request, and includes a holding means for holding an access address output together with the access request. a timer that starts timing in response to the output of the access request and stops the timing in response to the response signal; and a timer that responds to a timeout signal that is output when the timer measures a predetermined time. retry control means for performing a retry operation on the memory device based on the access address held in the holding means; and counting means for counting the number of retry operations in response to the timeout signal; It is characterized in that failure processing in the data processing device is performed when the count value of the means reaches a predetermined value.

Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram showing the configuration of an embodiment of the present invention.
In the figure, a data processing device 1 according to an embodiment of the present invention
includes a microprogram control unit 10, a memory request address/request factor holding register (hereinafter referred to as holding register) 11, a selector 12, and an OR circuit 13.
, a memory request flip-flop (hereinafter referred to as memory request FF) 14, a NOR circuit 15, 16, 20, a memory request monitoring timer (hereinafter referred to as monitoring timer) 17, and a retry counter 18. Decoder 19 and a faulty flip-flop (hereinafter faulty wF)
F) 21.

The data processing device 1 is connected to a system control device 2, and exchanges information with a memory device (not shown) via the system control device 2.

The operation of one embodiment of the present invention will be described below with reference to FIG.

The memory request address and request factor from the microprogram control unit 10 of the data processing device 1 are output to the holding register 11 and selector 12 via the signal line 101, and the memory request address and request factor are set in the holding register 11. At the same time, the signal is supplied to the system control device 2 via the selector 12 and the signal line 105.

Further, the memory request signal from the microprogram control unit 10 is output to the holding register 11 and the OR circuit 13 via the signal line 102, and at the same time, this memory request signal is used as a set signal in the holding register 11. OR circuit 13 and memory request FF
14 and signal lines 106 and 107 to the system control device 2.

The output signal from the OR circuit 13 has a logical value of "1" due to the memory request signal from the microprogram control unit 10.
This output signal with a logical value of "1" is output to the memory request FF 14 via the signal line 106, and is also output to the monitoring timer 17 and used as its start signal.

That is, the monitoring timer 17 starts counting up in response to a memory request signal from the microprogram control section 10.

An acceptance valid signal from the system control device 2 is input to the memory request FF 14 via the signal line 108, and the output signal from the OR circuit 13 input to the memory request FF 14 is held by this acceptance valid signal.

When a reply signal from the system control device 2 (reply signal from the memory device) is returned via the signal line 109 in response to the memory request signal, memory request address, and request factor from the microprogram control unit 10, this reply The signal is input to the microprogram control unit IQ, and is also input to the NOR circuit R15.
It is output to the monitoring timer 17 via the signal line 110 and used as its reset signal, and is also output to the retry counter 18 via the NOR circuit 16 and the signal line 111 and used as its reset signal.

That is, the monitoring timer 17 and the reset counter 18
The count value is reset by a reply signal from the system control device 2.

When no reply signal is returned from the system control device 2 in response to the memory request signal, memory request address, and request factor from the microprogram control unit 10, the monitoring timer 17 continues to count up until the count value reaches a predetermined value. When the timeout of the memory request is exceeded, the memory request timeout is detected and a logical value of "1" is sent to the retry counter 18 and the fault PF via the signal line 112.
21.

Also, at this time, the monitoring timer 17 outputs the logical value "o" to the NOR circuit 1i15 via the signal line 113, and the monitoring timer 1
7 is reset by the output signal from the NOR circuit 15 input via the signal line 110 at the next clock, and its count-up is stopped.

The retry counter 18 counts up by inputting the logic value "1" from the monitoring timer 17, and the signal line 1
The counter value is output to the decoder 19 via the signal line 114, and a logic value "1" is output to the selector 12 via the signal line 115 until the counter value reaches a preset specified number of times.

In the fault FF 21, the fault signal is set to the logic value "1" by inputting the logic value "1" from the monitoring timer 17, and the fault signal is outputted to the NOR circuit 2° via the signal line 118.

The decoder 19 decodes the counter value from the retry counter 18 and outputs the logical value "On" to the NOR circuit 20 via the signal line 116 until the counter value reaches a preset specified number of times, and outputs the logical value "On" to the NOR circuit 20 via the signal line 116. 0″ is also output to the microprogram control unit 10. Decoder 19
Then, when the counter value from the retry counter 18 reaches a preset designated number of times, the microprogram control unit 1
0 and the logical value “1” is output to the NOR circuit 20.

Noah episode F! A logic value “0” is input to @20 from one decoder via the signal line 716, and the faulty FF2
Since the logic value "1" is also input from 0 through the signal line 118, the memory request signal for retry outputted to the ORUgJ path 13 via the signal line 117 has the logic value "1".
“becomes.

This memory request signal for retry is OR circuit 13
, the output signal from the OR circuit 13 becomes the logical value M1'', and the memory request FF 14 and the signal line 1
07 to the system control device 2 as a memory request signal.

At this time, the monitoring timer 17 starts counting up again in response to the output signal from the OR circuit 13 inputted via the signal line 706.

Further, since the logical value "1" is input as a select signal from the retry counter 18 to the selector 12 via the signal line 115, the output signal from the holding register 11 input via the signal line 104 is selected, Holding register 11
An output signal from the memory request address and request factor is supplied to the system control device 2 via the signal line 105.

The system control unit r handles the memory request signal from the memory request FF 14 and the memory request address and request factor from the selector 12.
! When the reply signal from 12 is returned via the signal line 109, the monitoring timer 17 and retry counter 18 are reset, and the failure in which no reply signal was returned for the previously output memory request signal is determined to be an intermittent failure. Continue normal processing.

The system control unit y handles the memory request signal from the memory request FF 14 and the memory request address and request factor from the selector 12.
If the reply signal from 12 is not returned again,
Monitoring timer 17 overflows and retry counter 1
Count up 8.

The counter value of the retry counter 18 is output to the decoder 19 via the signal line 114, and the decoder 19 outputs a logic value "0" to the NOR circuit 20 via the signal line 116 until the counter value reaches the specified number of times. In order to do this, the OR circuit 13, the memory request FF 14, and the signal line 106.
107 and 117, a memory request signal for retry is output to the system control unit r112.

When the counter value of the retry counter 18 reaches the specified number of times, the decoder 19 outputs a logical value "1" to the NOR circuit 20 via the signal line 116, so the NOR circuit 20 suppresses the output of the memory request signal for retry. Ru.

Further, the decoder 19 outputs a logic value "1" to the microprogram control unit 10 via the signal line 116.

Since this output signal interrupts the microprogram control section 10 as a fault interrupt signal, the microprogram control section 10 accepts the fault interrupt signal and starts fault processing.

At this time, the microprogram control unit 10 outputs a logical value of "1" to the retry counter 18 via the signal line 103 during this fault processing, and the retry counter 18 is reset.

In this way, the supervisory timer 17 is activated in response to a memory request signal from the microprogram control unit 10, and each time the supervisory timer 17 detects a memory request timeout, the retry counter 18 is incremented and held. A memory request signal for retry is output using the memory request address and request factor held in the register 11, and when the counter value of the retry counter 18 reaches a predetermined number of times, the microprogram control unit 10 outputs a memory request signal for retry. By performing fault processing, it is possible to prevent device failure in the event of an intermittent fault and to continue normal operation.

Furthermore, when the counter value of the retry counter 18 reaches a preset predetermined number of times due to a fixed failure and interrupts the microprogram control unit 10, the operating channel may be abnormally terminated, a unit failure occurs, or a common part failure occurs. Therefore, the microprogram control unit 10 can treat this as a device failure.

1 As explained above, according to the present invention, when a predetermined time is counted by a timer that starts counting in response to an output of an access request from a data processing device to a memory device,
By performing a retry operation to the memory device using the retained access address, and performing failure processing in the data processing device when the number of retry operations reaches a predetermined value, intermittent This has the effect of preventing device failure in the event of a failure and allowing normal operation to continue.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Explanation of symbols of main parts 1...Data processing device 2...System control device 10...Microprogram control unit 11...
... Memory request address/request factor holding register 12 ... Selector 13 ... OR circuit 14 ... Memory request flip-flop 17 ... Memory request monitoring Timer 18...
...Retry counter 19 ...Decoder

Claims (1)

[Claims] (1) A failure handling method for a data processing device that receives a response signal from a memory device in response to an access request, which includes a holding unit that holds an access address that is output together with the access request, and a holding unit that responds to the output of the access request. a timer that starts measuring time in response to the response signal and stops the time measurement in response to the response signal; A retry control means for performing a retry operation on the memory device based on an access address, and a counting means for counting the number of retry operations in response to the timeout signal, wherein the count value of the counting means is a predetermined value. 1. A failure handling method characterized in that failure handling is performed in the data processing device when the value becomes a value.