JPS6128146B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a system for checking for failures that may occur in the occupancy control operation of a common bus in an information processing apparatus having a plurality of input/output devices.

() Background of the Technology In recent years, information processing devices have tended to include an increasing number of input/output devices. Along with this, data transfers have become more frequent, and the control of these operations has inevitably become more complex. This is because such data transfer is often carried out using a so-called common bus method in which a single bus is shared in a time-sharing manner.

Furthermore, in this case, a malfunction in one input/output device can affect many other input/output devices and processors. In other words, a failure may occur in which one input/output device is left monopolizing the common bus, but even if a reset is performed forcibly, the same failure will occur again. There is a large possibility that this will occur, and it may eventually lead to a stagnation in the processing of the entire information processing device.

() Prior Art and Problems Conventionally, the following check method has been used to detect such failures at an early stage.

The first method is to detect an error when a common bus acquisition request is generated and the next acquisition request is generated without being accepted.

The second method is to monitor the cycle at which the common bus occupier (input/output device) is switched, and detect it as an error if there is no change in the occupancy state for an unreasonable long period of time.

However, in the first check method, it is determined whether acquisition of the right to occupy the common bus was not carried out due to a failure of the device itself, or whether acquisition of the right to occupy the common bus was prevented due to a failure of another input/output device. I can't. The same applies to the second check method. Therefore, these conventional methods have the disadvantage that it is difficult to promptly perform drastic fault recovery measures when repairing, disconnecting, or replacing a faulty input/output device with a new one.

() Object of the Invention In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide a common bus check method that can clarify the location of a fault.

() Structure of the Invention According to the present invention, this object is to request acquisition of a common bus and exclusive right to the common bus, and when this request is accepted, to monopolize the common bus and perform data transfer. In a common bus fault check method for an information processing device including a plurality of bus masters, time is measured during a period during which at least one of the conditions is satisfied during the continuation of the acquisition request generated by each of the bus masters and the occupation of the common bus. a first monitoring means for monitoring the length of time from the time when the acquisition request is generated until the start of occupation of the common bus based on the output of the counting means; a second monitoring means for monitoring the length of time until the end of occupation of the common bus; and a configuration for sending the outputs of the first and second monitoring means from each of the bus masters to a predetermined one of the bus masters. and detecting a bus master that has occupied the bus for more than a specified time based on outputs from the first and second monitoring means from each of the bus masters, and acquiring the bus within a specified time after issuing the acquisition request. This is achieved by a common bus failure check system characterized in that it detects bus masters that have failed to perform the same operation, and detects bus masters that are causing the failure.

() Embodiments of the invention Examples of the invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram illustrating a portion of the check circuit according to the present invention that is provided corresponding to each input/output device, FIG. 2 is an operation timing chart of the circuit shown in FIG. 1, and FIG. 1 is a diagram showing an example of the configuration of an information processing device to which the circuit shown in FIG. 1 is applied.
Note that the same reference numerals are given to the signals and the signal lines that transfer the signals.

In the drawing, C is a counter, CLOCK is a clock signal input to counter C and its signal line, and *BSRQ indicates a request to acquire the exclusive right of the common bus in negative logic (logic "O" indicates the existence of a request). bus request signal and its signal line, *BSPR indicates in negative logic that occupancy of the common bus has been determined (logic "O" indicates that occupancy of the common bus has been determined) Bus priority The signal and its signal lines, NA, G ₁ and G ₂ are NAND gate circuits, I ₁ and I ₂ are inverter circuits, S ₁ is the output of counter C and decoded L first specified time
The first time detection circuit that detects T ₁ , S ₂ also decodes the output of counter C and detects the second specified time T ₂
L ₁ and L ₂ are the first and second error detection and holding circuits that have the function of holding the outputs of the NAND gate circuits G ₁ and G ₂ , MPU is the processor, and I/O #1 ...I/o#n is an input/output device,
MEM is memory and BUS is a common bus.

The second specified time T ₂ is, for example, 10 unit times (u
bus occupancy of less than 1 unit time during
If the design is such that 9 input/output devices and 1 processor are connected to a common bus,
The BUS can be used fairly, but it is determined according to the worst-case bus occupancy opportunities in these cases. That is, in this example, at least 9
This is because it is possible to occupy the bus for one unit of time by waiting for a unit of time, and the specified time T ₂ is given as 10 units of time, which is slightly longer than the sum of both. Furthermore, when controlling using priorities, a shorter time may be given to the items with higher priorities.

On the other hand, the first specified time is determined to be approximately equal to the value obtained by subtracting the bus occupancy time per time from the second specified time.

In applying this check method, it is necessary to specify how long the bus should be occupied under the worst-case conditions, and to set an upper limit on the bus occupancy time. It is necessary that at least one device is included. However, it is also possible to make limited use of it, such as invalidating the check results during operation with an exceptional device configuration.

Next, the operation will be specifically explained. First, before using the common bus, the bus request signal *BSRQ
is sent out, and as a result, the reset input of counter C is turned off, so that counter C starts counting operation. This corresponds to the operation at time _t1 in FIG. Next, when this bus request signal *BSRQ is accepted, a bus priority signal *BSPR is sent out. Therefore, in contrast to the period from the start of sending the bus request *BSRQ to the sending of the bus priority signal *BSPR, the NAND gate circuit _G1
A logic "0" is applied from AND gate A. Therefore, the bus priority signal *BSPR is sent within the specified time _T1 from the start of sending the bus request *BSRQ.
Once , the output of the first time detection path S ₁ is blocked by the NAND gate G ₁ and is no longer notified to the error detection circuit L ₁ .

In contrast, the bus priority signal *
If the arrival of BSPR is delayed and exceeds the first specified time _T1 , the specified time will be delayed as shown by the broken line in Figure 2.
The first error detection circuit L ₁ is notified via the NAND gate G ₁ of the first time detection circuit S ₁ that detected T ₁ ,
Generates the first bus error signal *BSER1. The same applies when there is no arrival of the bus priority signal *BSPR.

In addition, the output of the second time detection circuit S ₂ is the bus priority signal * when a specified time T ₂ has elapsed since the start of transmission of the bus request signal *BSRQ.
If BSQR continues, Nand Gate G2
The second error detection circuit L2 is notified through the error detection circuit _L2 .
That is, in FIG. 2, in normal operation, the priority signal * is activated at time _t5 as shown by the solid line.
The inverted signal BSPR of BSPR falls, but in the case of an abnormal operation, this signal remains, so the second bus error signal *BSER ₂ is sent out after the second specified time has elapsed, as shown by the broken line.

The first and second bus error signals *BSER1 and *BSER2 thus detected are used to clarify the location of the fault as follows. That is, the common bus is connected from the check circuit shown in FIG. 1 provided in each of the plurality of input/output devices I/o#1...I/o#n
The output to BUS *BSER1, *BSER2 is I/O
Selectively sent out according to address command signal, and same output for all input/output devices at the same time *
The logical product of BSER1 and *BSER2 (if either signal is “O”, “O” is output) is processed by the processor.
Notified to MPU. As a result, the processor MPU that has received notification of at least one of the bus error signals *BSER1 or *BSER2 accesses the input/output devices I/o#1...I/o#n in order via the common bus BUS. , notified bus error signal *BSER
1. Detect from which input/output device *BSER2 is issued.

Then, the location of the failure is determined depending on the following two cases.

(b) When bus error signals *BSER1 and *BSER2 are notified at the same time.

A failure that occurs because the input/output device that generated the second bus error signal *BSER2 occupied the bus for more than a specified time.

(b) Any one bus error signal *BSER1,
or *BSER2 is notified.

Either there is a failure in the bus acquisition control circuit in the input/output device that generated the first bus error signal *BSER1, or there is a failure in the bus occupancy control circuit in the input/output device that generated the second bus error signal *BSER2.

() Effects of the Invention As described above, according to the present invention, it is possible to easily detect the occurrence of an abnormality on the common bus and the location of its source.

In addition, since a counter and time monitoring circuit are provided individually for each input/output device, the specified time can be set individually depending on priorities, etc.
It is possible to closely monitor abnormalities. Furthermore, since two types of time monitoring are performed using the same counter,
Its circuit configuration is simple.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of a check circuit used in applying the check method of the present invention, FIG. 2 is a timing chart for explaining the operation of the check circuit shown in FIG. 2, and FIG. 3 is a diagram of the present invention. 1 is a diagram showing an example of the configuration of an information processing device to which a check method of the invention is applied; FIG. C...Counter, NA, _G1 , _G2 ...NAND gate circuit, _I1 , _I2 ...Inverter circuit, A...AND gate, _S1 ...First time monitoring circuit, _S2 ...Second
Time monitoring circuit, L ₁ ... 1st error detection circuit, L ₂
...Second error detection circuit, *BSQR...Bus request signal and its signal line, *BSPR...Bus priority signal and its signal line, *BSER
1, *BSER2...Bus error signal and its signal line, MPU...Processor, I/o #1 to I/O
o#n...Input/output device, BUS...Common bus,
MEM...Memory.

Claims (1)

[Claims] 1. Information processing that includes a common bus and a plurality of bus masters that request acquisition of exclusive rights to the common bus and, if this request is accepted, occupy the common bus and transfer data. In the common bus fault check method of the device, a counting means performs a time counting operation during a period during which at least one of the conditions of the acquisition request generated by each bus master being continued and the common bus being occupied is satisfied; first monitoring means for monitoring the length of time from the time when the acquisition request is generated until the start of occupation of the common bus based on the output of the means; and the length of time from the time when the acquisition request is generated until the end of occupancy of the common bus based on the output of the counting means; a second monitoring means for monitoring the first and second monitoring means from each of the bus masters, and configured to send the outputs of the first and second monitoring means from each of the bus masters to a predetermined one of the bus masters; Detecting a bus master that has occupied the bus for more than a specified time based on the outputs of the first and second monitoring means; detecting a bus master that has been unable to acquire the bus within a specified time after issuing the acquisition request; A common bus fault check method characterized by detecting a faulty bus master.