JPH01233861A - Transmission request signal transmission circuit - Google Patents

Abstract

PURPOSE:To prevent reduction in a data quantity sent between data terminal equipments by synthesizing the output of a delay means retarding a reception timing clock inputted with a separated carrier detecting signal by m-bit with a carrier detect signal to be separated and sending the result as a carrier detecting signal. CONSTITUTION:A reception section 2 is provided with a delaying means 3 and a synthesizing means 4 to synthesize a signal retarded by prescribed time from the received carrier detect signal and a signal not retarded. Since the carrier detecting signal with the simultaneous timing of ON of the carrier detect signal and with retarded OFF timing by a prescribed time is sent externally, even when the received carrier detect signal changes from ON to OFF, since the carrier detect signal sent externally is ON for prescribed time, the signal is fetched in an output data terminal equipment. Moreover, since the transmis sion section sends back the transmission enable signal at the same time with the transmission request signal, the reduction in the data quantity which can be transmitted within the prescribed time is eliminated.

Description

[Detailed Description of the Invention] [Summary] To prevent the amount of data transmitted between data terminal devices from decreasing, regarding a transmission request signal transmission circuit used when transmitting data between data terminal devices. In addition, for data terminal equipment that does not use a transmission permission signal, the purpose is to prevent data loss from being received, and when an on transmission request signal is input, it starts operating and manually transmits data to parallel data. a transmitter that converts the received envelope into an n-bit configuration using the transmission request signal and sends it out; and a receiver that separates the received n-bit envelope into received data and a carrier detect signal and outputs the same. a data transmission device comprising: a delay means for delaying the separated carrier detect signal by m bits of an input reception timing clock; and a synthesizing means for synthesizing the output of the delay means and the separated carrier detect signal. and a configuration in which the output of the combining means is sent out as a carrier detect signal.

[Industrial application field]

The present invention relates to a transmission request signal transmission circuit used when transmitting data between data terminal devices.

FIG. 4 is an explanatory diagram of the data transmission procedure.

In the figure, for example, data terminal device-1 (hereinafter referred to as data terminal device-1).

Transmission data sent from the DTE-1 (hereinafter abbreviated as DCE-1) is modulated by the line termination equipment-1 (hereinafter abbreviated as DCE-1), converted into an analog signal, and passed through the transmission line.

DC [! -2 and then converted back into data.

Sent to DTE-2. At this time, DTE-1 and DCE-
1 and between DTE-2 and DCC-2.
Data transmission is carried out in accordance with the TT recommendations and 24 transmission procedures.

An outline of this procedure will be explained below.

First, when transmitting data, the DTB-1 sends a transmission request signal (hereinafter abbreviated as R5) to the DCB-1, which is an indication of the desire to transmit data. Therefore, DCH-1 delays the Ils from DTE-1 until the other party is ready to receive it, and then sends a ready-to-send signal (hereinafter referred to as
Abbreviated as CS. ) as DT[! -1. As a result, transmission data (hereinafter abbreviated as 2SD) is sent from DTP-1, and DCE-1 is connected to the line and DCI.
Sends RS and SD to DTE-2 via E-2 (
(See right side of Figure 4).

On the other hand, DTB-2 detects received data when a carrier detect signal (hereinafter abbreviated as CD, but is the same as R3 in the transmitter) indicating that data to be received is input. (hereinafter abbreviated as RD, but it is the same as SD in the transmitter).

The above explanation is for the case of analog transmission between DCBs,
In the case of digital transmission, the DCH part has multiplexing and demultiplexing functions, but the transmission procedure is the same as above.

Now, when performing data transmission between DTE-1 and DTE-2 using such a procedure, DTE-1 and DT[! -2
In addition to being able to transmit as much data as possible within a predetermined time between DTE-1 and R3 and 8 ports at the same time, DTE-2 can capture the RO without missing it. is necessary.

[Conventional technology]

FIG. 5 is a block diagram of a conventional example, and FIG. 6 is an explanatory diagram of the operation of FIG. 5. Here, the symbols on the left side of FIG. 6 indicate the waveforms of the portions with the same symbols in FIG.

The operation shown in FIG. 5 will be explained below with reference to FIG.

(1) Transmitter (left side of Fig. 5 and Fig. 6 (see al)) When the turned-on RS is input, the delay circuit 11 delays R5 until the other party is ready for reception, and then the C
At the same time, this RS is used to operate a serial/parallel converter (hereinafter abbreviated as an S/P converter) 12.

And, for example, the 8 inputs of 2.4Kb/s are S/P
The converter converts it into 7-bit parallel data and adds it to the register 13. Since R5 is also added here, it is converted to an 8-bit envelope and sent to the multiplexer MUX (not shown).
Here, the data is multiplexed with other 8-bit envelopes to form data of, for example, 64 Kb, and sent to the transmission line.

The reason why the S/P converter 12 is activated with R5 being on is to prevent the S/P converter from operating and sending out something like SD when no SD is input.

(2) Receiving unit (see the right side of Fig. 5 and Fig. 6 (bl)) The received multiplexed data is separated by the demultiplexing unit DMUX (not shown) and converted into an 8-bit envelope, and then sent to the register 23. 7-bit P/S converter 22
and converted to serial data sequentially.

Output.

Here, when the register 23 becomes empty, even if the 7 bits transferred to the P/S converter still remain, the next 7 bits are taken in here and the corresponding CD is immediately output.

At this time, the CD was turned off.

Even if the data remaining in the P/S converter 22 is converted into serial data and output, it is not taken into the DTE-2.

Therefore, in order to prevent this, the C output from register 23
By delaying D by 1, for example, 14 bits as shown in FIG. 6(b)-CD in the delay circuit 21, P
All RDs remaining in the /S converter 22 are taken into the DTE-2. Note that the above operation is explained in detail in the embodiment using figures.

However, by delaying the CD by 14 bits.

When RS and SD are input to the transmitter at the same time, 14 bits at the beginning of RD are lost in the receiver. Therefore, in order to prevent this, the delay time of the delay circuit 11 of the transmitting section is shown in Fig. 6 (
a) If you set 1, for example, 21 bits like -C3, you will get Figure 6 (
As shown in b) I? D enters the ON part of the CD, and no data is lost.

[Problem to be solved by the invention]

However, there are some DTE-1s that do not see C3, but in such devices R3 and SO are sent out at the same time as shown in Figure 7(a), so the receiving section does not see C3 as shown in Figure 7(b). As shown in the figure, 14 bits of the first data of the RD are missing.

In addition, for DTIII-1 that looks at CS, there are two problems: dead time is introduced from RS on to CS on and SD sending, reducing transmission efficiency and reducing the amount of data that can be transmitted within a given time. There is a point.

[Means to solve problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, l starts operating when an on transmission request signal is input, converts the input transmission data into parallel data, and uses the transmission request signal to create an envelope of n bits (n is a positive integer). A transmitting section converts the data and sends it out, and 2 is a receiving section that separates the received envelope of n-bit structure into received data and a carrier detect signal and outputs them.

Further, 3 is a delay means for delaying the separated gear detect signal by m bits of the input reception timing clock, and 4 is a synthesizing means for synthesizing the output of the delay means and the separated carrier detect signal.

[Effect]

The present invention provides, when a data terminal device performs data transmission with another data terminal device via a transmitting section and a receiving section of a data transmission device, a delay means and a combining means are provided in the receiving section, and the received carrier detection signal is The result is a combination of one delayed for a predetermined time and one not delayed.

As a result, the above-mentioned carrier detect signals turn on at the same time, and the carrier detect signal whose turn off timing is delayed by a predetermined period is sent to the outside, so the received carrier detect signal turns on and off. Even after this happens, the carrier detect signal sent to the outside is still turned on for a predetermined period of time, so the output data is captured by the data terminal device.

Furthermore, since the transmitting section sends back the transmittable signal at the same time as the transmission request signal, the decrease in transmission efficiency caused by unnecessary delay is improved, and there is no decrease in the amount of data that can be transmitted within a predetermined time.

〔Example〕

FIG. 2 is a block diagram of the embodiment, and FIG. 3 is an explanatory diagram of the operation of FIG. 2.

Here, the delay circuit 31 is a component of the delay means 3, and the OR gate 41 is a component of the synthesis means 4. Note that the same reference numerals indicate the same objects throughout the figures. Hereinafter, the operation of FIG. 2 will be explained with reference to FIG. 3 assuming that the envelope has the same 8-bit configuration as in the conventional example.

(1) Transmitter (Figure 3 (al reference WI)) As soon as the ON RS is input, C8 is sent back.
), the rising edges of R3, C3, and SD coincide. Also, this R5 turns on the S/P converter 12, and the SD 7
The bits are converted in parallel by the S/P converter 12, combined with R3 in the register 13, and sent out as an 8-bit envelope.

(2) Receiving section (see Fig. 3(b)) The CD taken out from the register 23 and the CD delayed by a predetermined time in the delay circuit 31 are added together by an OR gate 41, and the resulting product is output as a CD signal to the outside. (See Figure 2).

Now, as shown in Figure 3(b)-■, 4 data rows (CD:
on), B data string (CD; on), no data for C.

(CD: OFF) is sequentially entered into register 23, and P/
Suppose that the signal is transferred to the S converter 22.

First, when the A data string enters the register 23, the ON CD
is immediately sent to the outside as shown in FIG. 3(b)-■, and the 7-bit data is transferred to the P/S converter 22, and the reception timing clock shown in FIG. 3(b)-○ is set. The signals are sequentially converted into series from this converter and sent out to the outside.

On the other hand, the register 23 becomes empty when the A data string is transferred to the P/S converter 22, so the last B data string is input and the ON CD continues to be output, so the serial data string is All De7 evenings are DTII! -2 (not shown).

Next, the B data string is sent to the P/S converter 2 in the same way as the A data string.
2 and is sequentially converted into serial data from this converter using the received timing clock and sent out to the outside.
There is no data in empty register 23, CO is off.
is entered, so as shown in Figure 3(b)-■, Figure 3(b)
-CD is turned off. Therefore, the R data string is DTB
-2 will no longer be included.

However, as shown in FIG. 3 (bl-■), the delay circuit 31.

For example, the ON CD delayed by 7 bits is the OR gate 41.
Sent via . Therefore, as shown in FIG. 3 (bl-■), all of the serial data of the B data string is taken into the DTE-2.

Here, the delay circuit 31 is constituted by one, for example, an n-stage shift register, and receives the output of the shift register. By making it possible to select up to Q7, it is possible to support an envelope with an n-bit configuration.

Also, the transmitting section is connected to I? as shown in FIG. 3(a). Since CS is sent immediately when S is input, the amount of data transmission is increased compared to the conventional example. Furthermore, for DTH-1 that does not see CS, the leading data of RO will not be lost.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the leading data of the RD can be prevented from being lost for the DTIE that does not see the CS.
This has the effect that there is no decrease in the amount of data transmitted within a predetermined time between 078 and 078.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment, Fig. 3 is an explanatory diagram of the operation of Fig. 2, Fig. 4 is an explanatory diagram of the data transmission procedure, and Fig. 5 is a diagram of the conventional example. A block diagram, FIG. 6 is an explanatory diagram of the operation of FIG. 5, and FIG. 7 is an explanatory diagram of problems in FIG. 5. In the figure, 1 is a transmitting section, 2 is a receiving section, 3 is a delay means, and 4 is a combining means. F? s, SD (shi) ■CD -1-Ko-Kaya 20
Erection lower mouth θ Tea 3 ■

Claims (1)

[Claims] When an ON transmission request signal is input, the operation is started, the input transmission data is converted into parallel data, and the transmission request signal is used to generate an envelope of n bits (n is a positive integer). A data transmission device comprising a transmitter (1) that converts the received envelope into a carrier detect signal and sends it out, and a receiver (2) that separates a received envelope of n-bit structure into received data and a carrier detect signal and outputs the separated data. a delay means (3) for delaying the carrier detect signal inputted by m bits of a reception timing clock; and a synthesizing means (4) for synthesizing the output of the delay means and the separated carrier detect signal, The synthesis means (4
) is configured to send out the output as a carrier detect signal.