JPH01236341A - Information processor - Google Patents

Abstract

PURPOSE:To easily detect the normal completion or abnormal completion of DMA transfer by comparing the value of a counter which performs addition/ subtraction on preset initial values every time when DMA is performed with the address at the time of DMA. CONSTITUTION:In order to make DMA transfer, a CPU 1 sets a start address in the address counter of a DMA controller 3 and, simultaneously in a counter 5, as well. When an IO controller 4 starts DMA transfer, a comparator 6 compares the contents of the address counter with counter 5 with each other and outputs a compared result to a flip-flop 7. When one DMA cycle terminates, the counted values of the address counter and counter 5 are increased or decreased by means of the content of a parameter register. When the compared result indicates discordance, the flip-flop 7 is set and the content is notified to the CPU 1. The CPU 1 recognizes the abnormal termination of DMA transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION 1. The present invention relates to an information processing device, and particularly to an information processing device using a direct memory access control method (hereinafter referred to as DMA control method). The present invention relates to an error detection method for checking whether data transfer has been performed correctly.

Conventionally, in this type of information processing apparatus, data transfer using the DMA control method has been performed as shown below.

That is, the central processing unit determines the address range on the main memory for performing data transfer by DMA (hereinafter referred to as DMA transfer), and sets the start address of the data transfer to the direct memory access controller (hereinafter referred to as DMA controller). Set the address counter, and set the length of the data transfer to the length counter of the DMA controller.

Further, the central processing unit outputs a command to the input/output controller (hereinafter referred to as IO controller) to start the DMAk transmission, including parameters as the case may be.

10 When the controller receives the command from the central processing unit, it outputs a DMA request signal to the DMA controller, and the DM
In response to this DMA request signal, the A controller outputs a bus use request to the bus arbitration circuit.

When the bus arbitration circuit receives a bus use request from the DMA controller, it arbitrates with the central processing unit or other bus use requests according to the priority, and outputs a bus use permission signal to the DMA controller.

When the DMA controller receives a bus use permission signal from the bus arbitration circuit, it outputs the contents of the address counter onto the address bus, outputs a memory access or write signal onto the control bus, and outputs a DMA permission signal to the IO controller. do.

When the IO controller receives a DMA enable signal from the DMA controller, it outputs data onto the data bus or writes the contents on the data bus to the data register.

Each time one DMA cycle ends, the address counter of the DMA controller is incremented or decremented, and the length counter is decremented.

The above processing operation is continued until the value of the length counter of the DMA controller becomes zero or until the DMA request signal is no longer output from the IO controller to the DMA controller.

When the DMA transfer is completed, if the length of the DMA transfer of the IO controller is known in advance, the central processing unit! checks whether the end address calculated from the length and start address matches the value read from the address counter of the DMA controller, and if the values match, it is considered to have completed normally. , if these values do not match, it is considered to terminate abnormally.

In the DMA control method in such conventional information processing devices, when the DMA transfer is completed, the central processing unit
Normal termination or abnormal termination was determined by checking whether the end address calculated from the DMA transfer length and start address of the 0 controller matches the value read from the address counter of the DMA controller. Therefore, if the length of the DMA transfer of the IO controller is not determined in advance, even if data is transferred to the wrong address on the main storage device due to a malfunction of the address counter of the DMA controller, the error cannot be detected. There was a drawback.

At this time, even if you try to find the end address by calculating the value of the length counter of the DMA controller, it is impossible to know whether the length counter is operating normally or not, and the result is either normal completion or abnormality. I couldn't decide if it was finished or not.

The present invention was made in order to eliminate the drawbacks of the conventional ones as described above, and is aimed at eliminating the disadvantages of the conventional ones as described above.
The present invention aims to provide an information processing device that can easily detect normal termination or abnormal termination even in A transfer.

An information processing device according to the present invention is an information processing device in which data is transferred to and from a main storage device by direct memory access, and each time the direct memory access is performed, data is set in advance. A counter that adds or subtracts an initial value; and a comparison unit that compares the value of the counter with the address at the time of the direct memory access to the main storage device, and when the comparison result of the comparison unit indicates a mismatch, the data is A feature of this system is that it notifies you of a transfer abnormality.

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 6, an information processing system according to an embodiment of the present invention includes a central processing unit 1, a main memory 2, a DMA controller 3, , 10 controller 4, counter 5, comparator 6, and flip-flop 7.

The central processing unit 1 is connected to the control bus 1 via the control signal line 111.
01, the address bus 102 via the address signal line 112, and the data bus 103 via the data signal line 113.

Main memory bag! 2 is connected to the control bus 10 via the control signal line 121.
1, the address bus 102 via an address signal line 122, and the data bus 103 via a data signal line 123.

The DMA controller 3 is connected to the control bus 101 via a control signal line 131, to the address bus 102 via an address signal line 132, and to the data bus 103 via a data signal line 133. Also, DM
The A controller 3 connects I via the DMA permission signal line 134.
It is connected to an O controller 4, a counter 5, and a flip-flop 7.

The To controller 4 is connected to the DMA controller 3 via a DMA request signal line 141 and a data signal line 142.
It is connected to the data bus 103 via.

The counter 5 is connected to the control bus 101 via a control signal line 151.
It is connected to the address bus 102 via an address signal line 152, and to the data bus 103 via a data signal line 153. Further, the counter 5 is connected to the comparator 6 via an address signal line 154.

Comparator 6 is connected to address bus 102 via address signal line 161 and to flip-flop 7 via comparison result signal line 162.

Flip-flop 7 is connected to central processing unit 1 via interrupt signal line 171.

Next, the operation of DMA transfer in one embodiment of the present invention will be explained.

The central processing unit 1 uses the main storage device 2 to perform DMA transfer.
The above address range is determined, and the start address is set in the address counter (not shown) of the DMA controller 3 via the address bus 102 and address signal lines 112 and 132, and the start address is connected to the address bus 102 and the address It is also set in the counter 5 via the signal lines 112 and 152. At this time, the central processing unit 1 connects the data bus 103 and the data signal lines 113.
3, the length of the DMA transfer is set in a length counter (not shown) of the DMA controller 3.

Also, central processing bags! 'l outputs a command to start DMA transfer, including parameters as the case may be, to the ■0 controller 4 via the data bus 103 and data signal lines 113 and 142.

Upon receiving the command from the central processing unit 1 , the controller 4 outputs a DMA transfer request signal to the DMA controller 3 via the DMA request signal line 141 .

In the DMA controller 3, the D from the IO controller 4
By receiving the MA request signal, a bus use request is output to a bus arbitration circuit (not shown) via the control bus 101 and the control signal line 131.

When the DMA controller 3 receives a bus permission signal that has been arbitrated with other bus requests according to priority in the bus arbitration circuit, it sends the bus permission signal to the address counter via the address signal line 132. The contents are outputted onto the address bus 102, a memory readout or write signal is outputted to the control bus 101 via the control signal line 131, and a DMA permission signal is sent to the IO controller 4 and counter 5 via the DMA permission signal line 134. flip flop 7
Output each.

The IO controller 4 uses this DMA permission signal to
Start the transfer and output the data to the data bus 103 via the data signal line 142, or output the data via the data signal line 1
42 to write the contents on data bus 103 to a data register (not shown).

At this time, the comparator 6 compares the content on the address bus 102 inputted via the address signal line 161 with the content of the counter 5 inputted via the address signal line 154, and outputs the comparison result via the signal line 162. and outputs the comparison result to the flip-flop 7.

When one DMA cycle is completed as described above,
The contents of the address counter of the DMA controller 3 are incremented or decremented, and the length counter is decremented.

Further, the counter 5 is also incremented or decremented at the end of the DMA cycle by the DMA permission signal inputted via the DMA permission signal line 142.

The increment or decrement in the address counter of the DMA controller 3 is determined by the contents of a parameter register built in the DMA controller 3, and the increment or decrement in the counter 5 is determined by parameters as well.

The above processing operation, that is, DMA transfer, is
Until the length counter of controller 3 becomes zero,
Alternatively, the process continues until the DMA request signal from the IO controller 4 is no longer output.

The flip-flop 7 records the comparison result from the comparator 6 every time a DMA cycle is performed, and is set when the comparison result indicates a mismatch. Further, the contents of the flip-flop 7 are notified to the central processing unit 1 via the interrupt signal line 171, and the central processing unit 1 can recognize the abnormal end of the DMA transfer by the notification from the flip-flop 7.

In this way, the contents on the address bus 102 during the DMA cycle and the value of the preset start address are transferred to the DM.
A comparator 6 compares the contents of the counter 5, which is incremented or decremented every A cycle, and when the comparison result shows a mismatch, the central processing unit 1 is notified of an abnormality in the DMA transfer via the flip-flop 7. By doing so, it is possible to easily detect normal termination or abnormal termination in a DMA transfer in which the termination address is not uniquely determined.

As explained above, according to the present invention, the address at the time of direct memory access to the main storage device and the value of the counter that adds or subtracts a preset initial value each time a direct memory access is performed. , and when the comparison result shows a mismatch, an abnormality in data transfer by direct memory access is notified.
Even in DMA transfer where the end address is not uniquely determined, there is an advantage that normal or abnormal end can be easily detected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Explanation of symbols of main parts 1...Central processing unit 2...Main storage device 3...Direct memory access (DMA) controller 4...Input/output ( 10) Controller 5...
... Counter 6 ... Comparator 7 ... Flip-flop

Claims (1)

[Claims] (1) An information processing device in which data is transferred to and from a main storage device through direct memory access, comprising: a counter that adds or subtracts a preset initial value each time the direct memory access is performed; Comparing means for comparing the value of the counter and the address at the time of direct memory access to the main storage device is provided, and when the comparison result of the comparing means indicates a mismatch, an abnormality in the data transfer is notified. An information processing device characterized by: