JPH01236499A - Semiconductor memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a semiconductor memory device with a redundant configuration, and furthermore, a semiconductor memory device having a redundant configuration so that the access speed when the redundant configuration is selected does not decrease compared to the non-selected state. Regarding redundant configuration technology,
For example, it relates to a technique that is effective when applied to repairing defective bits in SRAM (static random access memory).

[Prior art]

Techniques for improving the yield of semiconductor integrated circuits by introducing redundancy into chips can be used to repair defects in memory cells, which tend to increase as the degree of integration or storage capacity increases.

Conventionally, spare elements for replacing defective bits in semiconductor memory devices include spare rows (spare rows) including redundant word lines and spare columns (spare columns) including redundant bit lines as part of a memory cell array. It was composed of

When performing defect relief on semiconductor memory devices that include redundant configurations such as spare rows and columns, we focus on the memory cell array within the chip through wafer probe testing, etc., and perform memory cell address correspondence. to detect the location of the defective cell. The location information of the defective cells obtained in this way is stored in the fail memory built into the tester or external device, and a redundancy program is executed to replace the defective bits with defect repair bits according to the fail bit map stored in this memory. be exposed.

When a redundancy-programmed semiconductor memory device is supplied with an address to be rescued, the redundancy address decoder that determines the address prohibits the normal address decoder from selecting memory cells, and then selects the address that is included in the spare row or column. A preliminary decoder is used to address the defect relief bits that are to be repaired.

In addition, examples of documents describing redundant configurations include 19
There is r Nikkei Electronics JP P189-P2O1 published by Nikkei McGraw-Hill on July 21, 1980.

[Problem to be solved by the invention]

However, in the conventional redundant configuration using spare rows and columns, when an address to be rescued is supplied, after performing a special operation of prohibiting the memory cell selection operation by the regular address decoder, the spare row or spare column is Since the defective relief bits included in the column are addressed, it takes considerably more time to address the defective relief bits than when accessing a normal memory cell, and as a result, the semiconductor memory device The overall access time is forced to follow the relatively slow access time of the defect relief bit. This results in 1
Even if a semiconductor memory device is originally capable of high-speed access, once defective bits are repaired, the delay in access time for some of the defective repair bits causes the nominal access time of the entire semiconductor memory device to slow down. In terms of access time, there was a problem in that the version had to be downgraded.

An object of the present invention is to provide a semiconductor memory device with a redundant configuration that does not cause a delay in access time even when defective bits are repaired.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the selection is made based on the determination means that determines the input of the address to be repaired that is programmed to rescue a defective memory cell included in the memory cell array, and the output of the determination means according to the input address to be repaired. gate means, and an amplification device for amplifying data read out from a memory cell selected in the memory cell array to a common data line, and in which amplification output operation is prohibited in response to selection of the gate means. and a data holding means for replacing a defective memory cell connected to the output terminal of the amplifying means via the gate means to constitute a semiconductor memory device.

At this time, when the data holding means has a rewritable configuration in which the input terminal of the output buffer that outputs data to the outside and the output terminal of the input buffer that takes in data from the outside are commonly connected via gate means, At the time of writing, the switching timing of the gate means from selection to non-selection based on the output of the determination means is set to be the same as or earlier than the writing end timing 6 based on the control signal that defines the write operation to the memory cell. controlled.

[For production]

According to the above-mentioned means, when an address to be repaired is supplied, the operation of selecting a data holding means for replacing a defective memory cell can be performed by the time normal addressing of the memory cell is completed. This allows for a spare row of memory cells to be addressed before addressing them as in the conventional method.

Since there is no need to add a spare bit-specific operation such as switching to a spare column to the access operation for a normal memory cell, even if a defective bit is repaired, the access time of the repaired bit is not special. This is to prevent delays and achieve the same access time between those with and without defect relief.

When applying the redundant configuration according to the present invention to a rewritable semiconductor memory device, when writing data, the timing of switching the gate means from selection to non-selection based on the output of the determination means is determined by the write control for the memory cell. By setting the timing to be the same as or earlier than the writing end timing based on the signal, it is possible to relatively easily prevent erroneous writing to the data holding means for replacing the defective memory cell.

[Embodiment 1] FIG. 1 is a block diagram schematically showing the entirety of an SRAM which is an embodiment of a semiconductor memory device according to the present invention. Although the sRAM shown in the figure is not particularly limited, the sRAM shown in FIG.
It is formed on one semiconductor substrate using O8 integrated circuit manufacturing technology.

The SRAM shown in FIG. 1 constitutes a memory cell array 1 by arranging a plurality of static type memory cells (not shown) in a matrix.

Among the memory cells included in the memory cell array 1, the selection terminals of the memory cells arranged in the same row are connected to the word lines WL, ~WLh corresponding to the respective rows, and the selection terminals of the memory cells arranged in the same column are connected to the data input/output terminals. Connected to L6 to BLi and BLi.

The word lines WL and -WLh are connected to the row address decoder 2.
One of them is driven to the selection level by the output of
The selection operation is not particularly limited to the outputs BL, -BLi, and BLi of the row address buffer 3 that convert externally supplied row address signals A0 to Aj into internal complementary address signals; Load M
O8FET, and on the other hand, it is commonly connected to the common data lines CD, CD via a column switch element (not shown) included in the column selection circuit 4. Each column switch element (not shown) included in the column selection circuit 4 is switch-controlled by the output selection signal of the column address decoder 5, and this control operation is performed by internally complementing the column address signal A k = A n supplied from the outside. It is determined by the output of the column address buffer 6 which converts it into an address signal.

Therefore, the address signal A is applied to the SRAM of this embodiment.
When 0 to An are supplied, the data input/output terminal of a predetermined memory cell corresponding to this address signal is made conductive to the common data lines CD and CD via the column selection circuit 4.

An output terminal of a write amplifier 7 and a pair of differential input terminals of a differential amplification type sense amplifier 8 are connected to the common data lines CD, CD. Although not particularly limited, each of the write amplifiers 7 is supplied with write data externally supplied to the data buffer 9 in a single-ended manner, and based on this, drives the common data lines CD to a predetermined complementary level. . Although not particularly limited, the sense amplifier 8 is basically activated in response to a data read operation, and amplifies the complementary signal read out from the addressed memory cell to the common data lines CD, CD, thereby providing single-ended data. It is applied to the output buffer 10. Note that if the data input buffer 9 can directly drive the common data lines CD, the write amplifier 7 can be omitted.

A timing controller 11 performs basic timing control of the entire SRAM of this embodiment. For example, this timing controller 11 has a chip select signal C that instructs chip selection at a low level as an external control signal.
8, and a write enable signal WE instructing a write operation at a low level. This timing controller 11 is not particularly limited, but when a chip selection state is instructed, it controls the address buffer and address decoder to an operable state, and controls the operation of the write amplifier 7 at the timing when the addressing of the memory cell is determined. A write signal φW for selection or a read signal φr for selecting the operation of the sense amplifier 8 is asserted.

Although not particularly limited, the data input buffer 9 is controlled from a high impedance state to a state in which it can internally take in data in response to the assertion of the write signal φW to instruct a data write operation. Also,
Although not particularly limited, the data output buffer 10 is controlled from a high impedance state to a state capable of outputting data in response to assertion of a read signal φr to instruct a data read operation.

Next, a redundant configuration for relieving defective memory cells included in memory cell array 1 will be explained.

In the redundant configuration of this embodiment, the spare bits for replacing defective memory cells are basically different from the conventional configuration in which spare rows and spare columns are provided corresponding to the memory cell array. A spare bit is provided at the output terminal of the terminal and data manual buffer 9 to which data can be input/output.

That is, the reserved bit 13 is selected via the selection gate circuit 12.
The data input/output terminals of the sense amplifier 8 and the data input buffer 9 are connected to the output terminal of the sense amplifier 8 and the output terminal of the data input buffer 9, respectively.

Selection and non-selection control of the spare bits 13 via the selection gate circuit 12 is directly performed by the output of the redundant address decoder 14, although this is not particularly limited. The redundant address decoder 14 is programmed with the location information of the defective memory cell corresponding to the address in the memory cell array 1 through means such as cutting a fuse, and constantly decodes and monitors the input address signal to supply the address of the defective memory cell. In response to this, the redundancy selection signal RED is asserted to a selection level (high level). When the redundancy selection signal RED is asserted, the selection gate circuit 12 controls the data input terminal of the spare bit 13 to be conductive to the output terminal of the sense amplifier 8 and the output terminal of the data manual buffer 9, and performs a data read operation. Also, the activation of the sense amplifier 8 is inhibited. Activation control of the sense amplifier 8 by the redundancy selection signal RED is not particularly limited, but in the sense amplifier 8, a power switch (not shown) which is switch-controlled by the read signal φr is provided with a power switch which is switch-controlled by the redundancy selection signal RED. This can be achieved by inserting them in series. Although not particularly limited, FIG. 1 representatively shows a configuration corresponding to one spare bit 13.

FIG. 2 is a circuit diagram showing an example of the spare bit 13 and the selection gate circuit 12.

The spare bit 13 is a static flip-flop formed by cross-coupling the input and output terminals of a pair of complementary MO8 (hereinafter also simply referred to as 0MO5) inverters INVI and INV2, which are composed of a P-channel type MO8FETQ1 and an N-channel type MO3FETQ2. Consisted of.

The selection gate circuit 12 receives its input/output signal #! A write-only analog switch 16 is provided between the input/output signal line 15 and the output terminal of the CMOS inverter INV2, and an output terminal level of the CMOS inverter INVI is provided between the input/output signal line 15 and the output terminal of the CMOS inverter INVI. The analog switches 16 and 18 are controlled by a control logic 19.

The control logic 19 includes a redundancy selection signal RED and an inverted signal (hereinafter also simply referred to as an inverted write signal) of a write signal φW.
NAND gate NAND which controls the analog switch 18 by using W as two people, and redundancy selection signal TE.
A NOR gate NO that controls the analog switch 16 using the inverted signal of D and the inverted write signal φW.
It is composed of R.

In such a selection gate circuit 12, the redundancy selection signal RED
When is negated to a low level which is a redundant non-selection level, both analog switches 16 and 18 are controlled to be in an OFF state regardless of the level of the 1-inverted write signal φW. Therefore, since the spare bit 13 is made non-conductive with the signal line 15 at this time, the latch data of the spare bit 13 influences the memory cell data read by the access in either read access or write access of the memory cell. is not given, and the latch data is not rewritten by the access.

Further, when the redundancy selection signal RED is asserted at a high level, when the inverted write signal φW is set to a low level in response to a write operation instruction, the analog switch 16 is turned on, and the analog switch 18 is turned on. Controlled to off state.

Therefore, the write data taken in from the data input buffer 9 at this time is latched into the spare bit 13. In particular, since the analog switch 16 is controlled to be in the on state only during the period when the inverted write signal φW is asserted to a low level in synchronization with the change in the write signal φW that controls the write operation, the write signal φW
Even if the redundancy selection signal RED is asserted regardless of the write period defined by the assertion period of The possibility of erroneous writing to 13 is prevented.

Incidentally, in the configuration in which the data manual buffer 9 is controlled to a high impedance in response to the negation of the write signal φW as in this embodiment, changes in the write data are originally not captured internally. There is no problem in simply controlling the pair of analog switches 16 and 18 using the redundancy selection signal RED.

On the other hand, when the redundancy selection signal RED is asserted and the inverted write signal φW is maintained at a high level in response to a read operation instruction, the analog switch 1
6 is controlled to the off state, and the analog switch 18
is controlled to be on. As a result, the spare bit 13
The latch data is applied to the data output buffer 10 via the analog switch 18 and read out to the outside.

At this time, even in the read cycle, the sense amplifier 8 is deactivated in response to the assertion of the redundancy selection signal RED, and its amplification output operation is prohibited.

Therefore, the latch data of the spare bit 13 will not be disturbed by the read data from the defective memory cell.

In this way, when the address to be repaired is supplied to the SRAM from the outside, the operation of selecting the spare bit 13 to replace the defective memory cell is performed when the spare bit 13 is placed on the output terminal side of the sense amplifier 8. Because of its nature, it only needs to be done before the normal addressing of the memory cell is completed, and operations specific to the spare bit, such as switching the target to a spare row or column before addressing the memory cell, are not required. Since there is no need to add more to the access operation for a normal memory cell, even if a defective bit is repaired, the access time of the repaired bit will not be delayed compared to the access time of a normal bit. , the same access time can be obtained between those with and without defect relief.

[Embodiment 2] FIG. 3 is a circuit diagram showing another example regarding the selection gate circuit and spare bits.

In the circuit configuration shown in FIG. 3, the sense amplifier 2° is equipped with a pair of single-ended amplifiers in parallel, and provides a pair of outputs taken out from the amplifiers to the data output buffer 21 to read out the data externally in a single-ended manner. Further, the data manual buffer 22 supplies externally supplied data to the write amplifier 23 at a complementary level, and the write amplifier 23 drives the common data lines CD to the complementary level in accordance with the supplied data. Ru. Note that the data output buffer 21. The operation control for the data input buffer 22 and the write amplifier 23 is performed based on the read signal φr and the write signal φW as in the above embodiment, and the sense amplifier 20 is controlled based on the read signal φr and the redundancy selection signal RED as in the above embodiment. Its activation is now controlled.

In this embodiment, the spare bit 13 is constituted by a static flip-flop as in the above embodiment, but a pair of CMOS inverters INV1. I'N
The output terminal of V2 is commonly connected to a pair of output terminals of the sense amplifier 20 and a pair of output terminals of the data manual buffer 22 via analog switches 24 and 25. The pair of analog switches 24 and 25 constitute the selection gate circuit 26 in this embodiment, and are controlled in phase by the redundancy selection signal RED.

The selection gate circuit 26 of this embodiment always connects the complementary input/output terminal of the spare bit 13 to the complementary output terminal of the sense amplifier 20 and the data manual buffer 22 while the address to be relieved is supplied and the redundant selection signal RED is asserted. The complementary output terminals are controlled to be conductive, but when an address to be rescued is supplied and a read operation is instructed, the amplified output operation of the sense amplifier 20 is controlled by the redundancy selection signal RED.
Since the latch data of the spare bit 13 is inhibited in response to the assertion period of , the latch data of the spare bit 13 will not be confused by the data read from the defective memory cell.

Furthermore, since the data input buffer 22 is controlled to have a high impedance in response to the negation period of the write signal φW, changes in the write data are originally not taken into the internal memory, so the address to be rescued is supplied. When a write operation is performed under this condition, a change in the write data that is allowed under the timing rule will not be undesirably transmitted to the spare bit 13 and the normal data will not be erroneously rewritten.

In this embodiment as well, as in the first embodiment, defects can be repaired without undesirably transmitting changes in write data permitted by timing rules to the spare bit 13 and erroneously rewriting normal data. SRAM not included
The same access time is obtained.

[Embodiment 3] FIG. 4 is a circuit diagram showing the main part when a plurality of selection gate circuits and spare bits are provided.

For example, i bits of spare bits 301 to 30i and i selection gate circuits 3 in one-to-one correspondence with each spare bit.
1□ to 31i, the selection gate circuits 311 to 31i are provided.
The redundancy selection signal RED~REDi that controls 31i is
The address to be rescued is output from a programmed redundant address decoder (not shown), and one redundancy selection signal corresponding to the programmed address to be rescued is asserted in response to the input of the programmed address to be rescued according to the redundancy program state. Further, the control signal for inhibiting the amplification output operation of the sense amplifier 20 in the read cycle can be the OR signal φred of the redundancy selection signals RED and -REDi.

In this embodiment, not only the effects of the above-mentioned embodiments can be obtained, but also defects in multiple bits can be repaired.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

For example, in the above embodiment, the output of the redundant address decoder is directly used to control the selection of the selection gate circuit and the deactivation control of the sense amplifier during the read cycle, but the present invention is not limited to this, and the output of the redundant address decoder is The signal may be adjusted inside the timing coat roller based on the read cycle timing or write cycle timing and then supplied as the selection signal of the selection gate circuit or the activation control signal of the sense amplifier. Therefore, in this case, there is no need to include control logic 18 as shown in FIG. 2 in the selection gate circuit.

In the above explanation, the invention made by the present inventor was mainly applied to SRAM, which is the field of application that formed the background of the invention, but the present invention is not limited to this, and the present invention is not limited to this. The present invention can be applied to various semiconductor storage devices such as ROM (access memory) and ROM (read-only memory).

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, the data holding means for replacing defective memory cells is
Since it is provided on the output terminal side of the amplification means such as a sense amplifier or main amplifier for amplifying memory cell data, it selects a data holding means to replace a defective memory cell when an address to be repaired is supplied. This only needs to be done before the normal 7 addressing for the memory cell is completed, and the operation specific to the spare bit, such as switching the target to the spare row or column before addressing the memory cell, is normal. By not requiring any additional access operations for memory cells,
Even if defective bits are repaired, the access time of the repaired bits is prevented from being particularly delayed, and the same access time can be obtained between the defective bits with and without the defect repair. .

In addition, when applying the redundant configuration according to the present invention to a writable semiconductor memory device, when writing data, the operation period for selecting data holding means for replacing defective bits is
If control is performed based on a write control signal for memory cells, there is a risk that a change in write data that is permissible based on timing rules may be undesirably transmitted to the data holding means for replacing defective bits, and normal data may be erroneously rewritten. can be prevented relatively easily.

By eliminating the need for spare rows and columns in the memory cell array, there is no need for circuits such as spare decoders that correspond to them, leading to smaller chip size and data retention for replacing defective memory cells and defective bits. There is no strict restriction on the timing of switching the selection of the means, and as a result, the switching control procedure and the circuit configuration therefor can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the entire SRAM which is an embodiment of the semiconductor memory device according to the present invention. Figure 2 is a circuit diagram showing an example of a spare bit and selection gate circuit, Figure 3 is a circuit diagram showing another example of a spare bit and selection gate circuit, and Figure 4 is a circuit diagram showing an example of a spare bit and selection gate circuit. FIG. 3 is a circuit diagram showing main parts when provided. DESCRIPTION OF SYMBOLS 1... Memory cell array, WL, ~WLh... Word line, 2... Row address decoder, 3... Row address buffer, 4... Column selection circuit, 5... Column address decoder, 6 ... Column address buffer, 7... Write amplifier, 8... Sense amplifier,
9... Data manual buffer, 10... Data output buffer, 11... Timing controller, 12...
- Selection gate circuit, 13... Reserve bit, 14...
Redundant address decoder, RED...redundant selection signal, φ
r...Read signal, φW...Write signal, φW...
・Reverse light signal. CD, CD-...Common data line, BL,, BLo-BL
i, BLi...Bit line, 16.18...Analog switch, 19...Control logic, 20...Sense amplifier. 21...Data output buffer, 22...Data manual buffer, 23...Write amplifier, 24.25...
- Analog switch, 311-31i... selection gate circuit, RED1-REDi... redundancy selection signal.

Claims (1)

[Claims] 1. A memory cell array in which a plurality of memory cells are arranged in a matrix, a determination means for determining input of an address to be repaired programmed to repair a defective memory cell included in the memory cell array, and a repair method. gate means selected based on the output of the determination means corresponding to the address input to be performed; and the gate means amplifies data read out from the selected memory cell in the memory cell array to the common data line. The memory cell comprises an amplification means whose amplification output operation is inhibited in response to the selection, and a data holding means for replacing the defective memory cell coupled to the output terminal of the amplification means via the gate means. A semiconductor memory device characterized in that it is a semiconductor memory device. 2. The data holding means has a rewritable configuration and is commonly connected to the input terminal of the output buffer that outputs data to the outside and the output terminal of the input buffer that takes in data from the outside via the gate means, The switching timing of the gate means from selection to non-selection based on the output of the means is controlled to be the same as or earlier than the write end timing based on a control signal that defines a write operation to the memory cell. A semiconductor memory device according to claim 1, characterized in that: