JPH012364A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to semiconductor devices, particularly SI using compound semiconductors.
S)' It relates to field effect transistors (NET) having a hetero interface such as HT and MIS FET.

(Summary of the Invention) The present invention has a first semiconductor layer with a narrow bandgap and a second semiconductor layer with a wide bandgap, and has a predetermined position at the interface between the first semiconductor layer and the second semiconductor layer. In a semiconductor device in which a source region and a drain region are formed with an interval of , and a gate electrode is formed on a second semiconductor layer between the source and drain regions, the source region and the drain region By configuring the first semiconductor layer to be separated by a second semiconductor layer in contact with the first semiconductor layer, a short channel device can be manufactured with high precision.

(Prior art) Figure 3 shows a conventional n'''-GalnAs gate SIS (
Semiconductor jnsulaLor S
em1conductor ) FET.

This SIS Ft! As for the manufacturing method of T, first, Fig. 3A
As shown in Fig. 1, a chamfer forming layer with a thickness of 10 is formed by sequential epitaxial growth on a semi-insulating 1nP substrate +1+.
Undoped Ga1nA with a narrow bandgap of about 0
srjf (2), a wide bandgap undoped 8 lInAs film with a thickness of about 500 mm (31) and an impurity'11 with a thickness of about 2000 mm (31 mm) to serve as the gate electrode.
1 degree 5 X IQl″cm-', +l [!degree n ''-
Ga InAs 1 (41) is deposited.

Next, as shown in FIG. 3B, n''-GaInAsM
After patterning f41 to form the gate 'd1 pole (5), the gate voltage pli+51 is applied as shown in FIG. 3C.
Using a mask as a mask, an n-type impurity such as Si is ion-implanted using a self-line, and activated by annealing at about 700° C. to form an n3-type source region (6) and a train region (7) in the undoped GaInAs1cif (21).

Next, as shown in the third diagram, the source area 1!3. (6
Ohmic electrodes (8) in 1 and train region (7), respectively.
and (9) to obtain SIS PET (10).

[Problem that the invention seeks to solve]

In the SIS FET (10) with the above configuration,
The distance between the source region (6) and the drain region (7) corresponds to the effective gate length.
7) has the property of penetrating inside as shown by the broken line (11) in FIG. 4, which makes it difficult to fabricate short channel (small gate length) devices.

The present invention addresses the above points and provides a semiconductor device in which a short channel of 411 degrees can be obtained well.

[Means for solving problems]

The present invention has a first semiconductor layer (2) with a narrow bandgap and a second semiconductor layer (3) with a wide bandgap,
A source region (14) and a drain region (15) are formed at a predetermined interval at the interface with the second semiconductor layer (3) in the first semiconductor layer (2). In a semiconductor device in which a gate electrode (5) is formed on a second semiconductor layer (3) between drain regions (15), a source region (14) and a drain region (15) are formed on the same semiconductor layer (13). The first semiconductor layer (2
) is separated by the second semiconductor layer (3) in contact with the second semiconductor layer (3).

[Effect]

The source region (14) and drain region (15) are formed of the same semiconductor [(13) without using ion implantation. After forming the source vA region (14) and drain region (15), the second semiconductor layer (3) and gate electrode (5) are formed by epitaxial growth at a temperature lower than the annealing temperature after conventional ion implantation. . Therefore, redistribution of the source MJ5 (14) and drain region (15) is small and a short channel device can be obtained with high precision.

Further, since the impurity concentration of the source region (14) and drain region (15) can be made higher than that of the ion implantation layer, the source resistance can be lowered.

Furthermore, a source region (14) and a drain region (15)
is the first semiconductor rti (the second semiconductor J# in contact with 21
Since the signals are separated by +31, the so-called rectangular channel effect can be suppressed.

〔Example〕

Hereinafter, an example of the semiconductor device of the present invention will be explained along with its manufacturing method with reference to FIG.

First, as shown in Figure 1A, a semi-insulating 1nP 4 slope (1
On top of 1 is an undoped Ga1nAs layer (2) with a narrow bandgap of about 1000 nm thick, which becomes a channel forming layer, and on it is a 500 nm thick undoped Ga1nAs layer (2), which becomes a source region and a drain region.
About 1 person. An n''-GalnAs layer (13) with an impurity concentration of about 5 x 1011''cm-' is formed by epitaxial growth.

Next, as shown in FIG. 2B, n of the part corresponding to the gate is
The ``-GalnAs layer (13) is selectively etched away. At this time, the Ga1nAs layer (2) is slightly over-etched.
A source region (14) and a drain region (15) made of GalnAs are formed.

Next, as shown in FIG. 1C, a second epitaxial growth is performed to form an undoped G1nAs layer +31 with a wide bandgap of approximately 500 nm thick, which will become an insulating layer, and an impurity concentration layer of approximately 2000 nm thick, which will become a gate electrode. degree 5×101
An n''-GalnAs layer (41) of the order of 'am-' is formed.

In this second epitaxial growth, undoped GalnAs1w (16
) and then undoped A11nAsJii.
f(3) and n”-Ga I nAsjif (41
The hetero interface becomes better when grown.

In the epitaxial growth process of FIG. 1C (or FIG. 2), the already formed source er1kfi (
14) and the drain region (15) are also subjected to a thermal process,
Since the growth temperature can be as low as about 600° C., seepage from the source region (14) and drain region (15) is small.

Next, as shown in the first diagram, an n”-GalnAs layer (4
), for example, a photoresist (18) is embedded in the recess (17) corresponding to the cage part.

Then, this photoresist (18) is masked and the other n''-Ga1nAslj# (41) is selectively etched away using serif alignment to form a gate electrode (5) made of n''-GalnAs.
A window is opened in the S layer (3), and a source electrode (8) and a train electrode (9) are formed by contacting the source region (14) and drain region (15), respectively. By doing so, as shown in the first diagram, the undoped Ga InAs layer forming the Nayan metal layer is formed.
(A source region made of n′″-GalnAs on 21 (
14) and a drain region (15) are formed, and the source region b39 (14) and the train region (15) form an AlIn layer with Ga1n^s1m (21) in the gate part.
The target sls are separated from each other by an As layer (3).
Obtain POT (19).

In the SIS FET (19) having such a configuration, the source region (14) and drain region (15) are not implanted by ion implantation but by epitaxial Twit.
- Formed as a GalnAs layer (13), and then epitaxially grown twice in L1 to become a one-color edge layer t.
3) and gate electrode n''-GaInAs1j4+
41. Since the growth temperature at this time is as low as about 600.degree. C., there is little redistribution of the source region (14) and drain region (15), so that a short gate length SIS FE'r can be obtained with high accuracy.

Furthermore, since the impurity concentration of the source region (14) and the train region (15) can be made to be +11i higher than that of the layer formed by ion implantation (l Q" cm in the case of ion implantation)
The source resistance can be lowered by approximately 10"am"3) for Ga1nAs.

Also, shallow source region (14) and drain region (15)
can be easily formed, so short channel '21J effects can be suppressed.

In the above example, semi-insulating 1nPJJ+& is used to make Ga1nA
s channel layer, 8l 1nAs insulating layer, n''-
GalnAs source and drain regions, n”-G
Although the structure was constructed by forming a gate electrode of alnAs, other compound semiconductors such as semi-insulating GaAs could be used to form the gate electrode.
aAs channel layer, AlGaAs insulating layer, n”
-GaAs source and drain regions, n''-G
A configuration in which an aAs gate electrode is formed can also be used.

In addition, in the above example, a highly concentrated semiconductor layer was used as the gate electrode, but instead of this, a configuration MIS (Metal Insulator) using a gate electrode made of a metal such as
rSe+*1conductor) NET.

Furthermore, although the above example is an n-channel type, it can also be configured as a p-channel type.

(Effects of the Invention) According to the present invention, the source region and the train region are formed of the same semiconductor layer, and the second semiconductor layer (so-called insulating N) in contact with the first semiconductor layer (so-called Nayannel formation layer) is formed of the same semiconductor layer. By having a separate configuration, similar channels such as 513Fl:T and old 5FET can be manufactured with high precision.

Moreover, the source resistance has been reduced, and the short channel effect has been suppressed.
It will be done.

[Brief explanation of the drawing]

1A to 1E are cross-sectional views showing an example of a semiconductor device according to the present invention in the order of manufacturing steps, FIG. 2 is a sectional view showing another example of the process of FIG. 1C, and FIGS. 3A to 3D are conventional FIG. 4 is a sectional view showing an example of a semiconductor device in the order of manufacturing steps, and FIG.
It is an lr side view. +1) is treated as semi-insulating 1nP base, (2) is undoped Ga
lnAsJ-, (3) is undoped ALInAsr,
(5) is the gate electrode, (13) is n”-GalnAs
The layer (14) is a source region, and (15) is a drain region.

Claims (1)

[Scope of Claims] It has a first semiconductor layer with a narrow bandgap and a second semiconductor layer with a wide bandgap, and a predetermined layer is formed at the interface between the first semiconductor layer and the second semiconductor layer. At intervals,
In a semiconductor device in which a source region and a drain region are formed, and a gate electrode is formed on the second semiconductor layer between the source region and the drain region, the source region and the drain region are made of the same semiconductor layer, A semiconductor device separated from the first semiconductor layer by the second semiconductor layer in contact with the first semiconductor layer.