JPH01236817A - Pulse counter - Google Patents

Abstract

PURPOSE:To correctly read a counter value with a small software load by prohibiting the register value updating of plural registers while the register value of plural registers is read after the register transfer completion with a processor. CONSTITUTION:While a processor 5 divides and reads registers 41-43, register value updating is prohibited. Thus, even when a counter 3 is changed during the dividing and reading, the processor 5 can correctly divide and read the value before the counter value is changed and a conventional erroneous reading is prevented. Since a register value reading starting is executed after the register transfer completion, a stable counter value can be read and a conventional 'double reading' is made unnecessary.

Description

[Detailed Description of the Invention] [Summary] A pulse counting device in which a processor V divides the value of the counter into upper and lower parts and reads it out when the bit length of the counter is longer than the data bus length of the processor. Even if there is a pulse input during the counter read period and the counter value changes, the purpose is to read the counter value accurately with a relatively small software load. When transferring the counter value to multiple registers, the register transfer timing and the counter input pulse timing to the counter are synchronized so that the counter value does not change during register transfer. and a register update control circuit that prohibits updating of the register values of the plurality of registers during the period when the processor is reading the register values of the plurality of registers after register transfer is completed.

[Industrial application field]

The present invention relates to a pulse counting device in which the bit distribution of the counter is better than that of the data bus of the processor, and a setter divides the value of the counter into f2 numbers such as upper and lower. .

In the pulse counting device of the present invention, for example, an observation device such as a flow rate 81 or a thermometer transmits data in the form of a pulse number, and a processor reads the pulse count value gIn and reads the counter value at a certain timing. This is used in systems that monitor changes in data volume by comparing the current value with the current value. In a system that uses such a processor to read the counter value, it is necessary to read the b counter value accurately with as little software load as possible.

[Conventional technology]

Conventionally, there is a system that transmits change data from observation devices such as flowmeters and thermometers as pulse numbers, and centrally monitors the data using a processor. This system is shown in FIG.

The input pulse is input to the counter 3. Is counter 3 an output buffer with the width of the data bus? (The registers 4I to 43 are written in m. The processor 5 operates the address decoder 6 and reads out each output buffer sofa 41 to 43 in order.

FIG. 7 shows a flowchart for reading out the processor 4). The processor 5 that read each output h buffer,
In step (2), the data input to the register is stored in the memory within the processor 5 (MAI to MCI).

In step (2), it is determined whether the previous stored values MA2 to MC2 are present or not, thereby determining whether or not the first reading has been performed. In steps ■～■, the current read data values MA1～MC
1 and the previous read data values MA2 to MC2. If the comparison results do not match in step ■, replace the current read values MAI~MCI with the previous read values MA2~M.
It is stored in the memory in Broselli°5 as C2. If the comparison results match in step (2), the previous read values MA2 to MC2 in the memory in the processor are cleared.

The counter value is fln every time a pulse is input, the processor reads the counter value by limbling at a certain timing, and monitors changes in the amount of data by comparing the previous value and the current value. In such a system, the period during which the state of the counter is changing is the so-called state transition JI! If the timing at which the processor reads the counter value coincides with the timing at which the processor reads the counter value, the value read by the processor will be a different value from the actual counter value, and will not mean that an accurate value has been read.

That is, as shown in FIG. 4, if the counter value is rollLl when the pulse input occurs, when the -V error occurs in the first digit (
When a pulse is input to the counter), the counter value is rollo
, I, and then when the second digit 1179 occurs, the counter value becomes rolooJ, and finally the counter value becomes rio.
oo-+, and in this way, from the counter value 1[111J to I1000J, the counter value ro110. l
After the state transition period of rolooJ, if the processor reads during this state transition period, the counter value that it originally wants to read is rloooJ. Counter value r0110. It leads to I or roioo, +.

Conventionally, in order to obtain an accurate counter value, the counter value is read twice, and the value read the first time and the value read the second time are compared and if they do not match (
iIA is 11'0110J once.

2nd time r0100. I) does not capture this counter value,
If they match (first r1000.l, second rlooo
OJ) performs so-called r2'[ff reading] processing to take in this counter value as a true value.

In this way, even if the processor reads during the state transition period of the counter, the counter value at this time is not taken in, but only the accurate value can be taken in.

On the other hand, conventionally, the pit length of the counter (for example, 16 bits)
In a system where the counter value is longer than the data bus length of the processor (for example, PA is 8 bits), the processor needs to read the counter value by dividing it into, for example, the first and lower parts. For example, rooooooool 11 where the counter value is 16 bits.
111111 When reading J, the processor reads T
fR first reads the lower rllllllllllJ, then reads the upper roooooool, l, and reads the 16 bits in 8-bit units. When such a first read is completed, a second read is performed. As described above, if the 16-bit counter value read the first time and the 16-bit counter value read the second time match, that counter value is taken in as the true value.

(Problems to be Solved by the Invention) The conventional device described above performs so-called [read twice and I processing] in order to prevent the processor from reading the counter incorrectly, so the software load increases accordingly and the program is ? ! There was a problem with having two males.

Also, as stated above, if you apply "Read twice JfI!ll!J!" to the method of dividing the counter value into upper and lower parts and reading it, the read timing of the processor and the counter state R transition period will be reduced by that amount. This increases the probability that the two will overlap, and the probability that the "read twice and process once" will fail also increases.

For example, as shown in FIG. 5, when the pit length of the counter is 16 bits and the data bus length of the processor is 8 bits, the counter value is rooooooo.

At 111111111J, the processor
There is a pulse input between reading 11111111.1 and reading the next upper byte, and the counter value is r.
Suppose that it changes to oooooool 000000000.1. In this case, there is no problem if the counter value does not change during the processor's counter read period, but if the counter value changes during the processor's counter read period as described above, the processor stores the lower byte as N1111111.
While leading with J, the upper byte is roooooo.

10J is read, which does not mean that the counter value was read correctly.

Even if the first lead is a false lead like this, “2
If you perform the "counter reading" process, the second reading will be correct as long as the counter value does not change, and if the b counter value does not change after that, the first and second counter values will match and the counter will eventually be correct. Values can be imported.

With such conventional devices, [Due to reading twice and processing once, it takes time to read the counter value correctly after the counter value changes, which makes it impossible to perform processing in a short time.] was there.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pulse counter device that can accurately read a counter value with a relatively small software load even if a pulse input occurs during one set of counter read periods and the counter value changes. .

[Means to solve the problem]

The present invention has a plurality of registers provided between a counter and a processor υ corresponding to the number of a plurality of bit groups, and when a counter value is transferred to a plurality of registers, the counter value changes during register transfer. A pulse synchronization circuit synchronizes the register transfer timing and the counter input pulse timing to the counter so that the register transfer timing and the counter input pulse timing to the counter do not change. It consists of a register update 11111 circuit that prohibits updating.

[nm]

In the present invention, updating of the register value is prohibited while the processor is reading the register value for t1. Therefore, even if the counter value is changed during divided reading, the processor can correctly divide and read the value before the counter value change, and erroneous reading as in the conventional example does not occur. In addition, since register value reading starts after the register transfer is completed, stable counter values can be read, and "2
No need to read twice.

〔Example〕

FIG. 1 shows a block diagram of the present invention.1. In the figure, reference numeral 1 denotes a pulse input terminal through which pulses for sequentially changing the counter value are input. , 2 is a pulse synchronization circuit that prevents pulses from being input to the counter at the timing when the counter value is transferred to the register, and after the counter value has been transferred to the register, it inputs pulses to the counter until the next register transfer. This is a latch circuit that synchronizes pulse input and register transfer. 3 is a 24-bit counter, for example, and the counter value is changed every time a pulse is input using the output of the synchronization circuit 2 as a clock.

41 and 42.4g are, for example, 8-bit registers, which are supplied to the processor 5 via the output data path of the counter 3. The processor 5 sequentially specifies the addresses associated with the registers 41 to 43, sequentially reads the values of the registers, and keeps the counter running until all the values of these three registers 41 to 43 have been read, as will be described later. It is controlled via the register update $ control circuit 7 so that the output of No. 3 is not transferred to each register 41 to 43. 6 is an address decoder, which decodes the address code of each register designated by the processor 5 and controls the read timing of each register 41 to 41;
Due to Il, the so-called counter read period from reading the register 41 to reading the register 43 registers 41~
A control signal for stopping the data transfer of 43 is supplied to the register update control circuit 7.

The register update control circuit 7 causes the registers 41 to 43 to perform a transfer operation in synchronization with the output clock of the clock generator 8, and stops the data transfer operation of the registers 41 to 43 in response to a control signal from the address decoder 6 during the counter read period. The clock generator 8 is a circuit that outputs a clock for synchronizing the operations of the pulse synchronization circuit 2, the processor 5, and the register update control circuit 7.

Next, the operation of the apparatus having the above configuration will be explained with reference to the operation timing chart shown in FIG.

The clock a taken out from the output clock generator 8 is supplied to the pulse synchronization circuit 2, and on the other hand, the pulse b that comes into the terminal 1 at a timing unrelated to the timing of the output clock a is also pulse synchronized. Supplied to circuit 2. In the pulse synchronization circuit 2, the rising timing of the pulse b and the rising timing of the pulse a (that is, registers 41 to 41 to be described later)
43), and is taken out as a counter input pulse C and supplied to the counter 3.

The counter value d of the counter 3 is changed at the rising timing of the counter input pulse C, and in this case, for example, it is changed sequentially from N to <N-11) and then from (N+1) to (N+2).

On the other hand, the clock a is also supplied to the register update control circuit 7, and a data latch signal e is generated such that the rising timing and falling timing of the clock a correspond to the opposite relationship.
is taken out. The data latch signal e is a signal whose counter value performs a data transfer operation to the registers 41 to 43 at its rising timing. Here, counter input pulse C
Before the occurrence of the counter value d, the counter value d is N, so the counter value N is transferred to the registers 41 to 43 at the rising timing of the data latch signal e, and when the counter input pulse C occurs, the counter value d becomes (N+1 ), so
The counter value (N + 1) is transferred to the registers 41 to 43 at the rising timing of the data latch signal Me immediately after the rising timing of the counter input pulse C.

In this way, the pulse synchronization circuit 2 synchronizes the timing of pulse b with the register transfer and synchronizes the timing of pulse b with the counter input pulse C.
Since the counter value is transferred to the registers 41 to 43 (at the rising edge of the data wrap signal @e), no pulse is input to the counter 3, and the counter value is transferred to the register. After this is completed, a pulse is manually input to the counter 3 (counter input cabal C). Therefore, at the timing when the value of the counter 3 is transitioning (the rising timing of the pulse C), the register 41
.about./43, the correct counter value of the counter 3 cannot be copied to the registers 41-43, but according to the present invention, the correct counter value of the counter 3 can be copied to the registers 41-43.

Next, the output reading of the registers 41 to 43 by the processor 5 will be explained. Now, when the counter value of the counter 3 is (N-+i), the control signal A1 is taken out from the address decoder 6 by the 7 address specification to the processor 5, and the output 8 pin 1- of the register 4I is sent to the processor 5 via the data bus. Suppose that it is supplied to and read. In this case, since the processor 5 is supplied with the output clock a of the clock generator 8, the start timing of reading the register 41 is the register 4! ~43 data latch signal e
It is synchronized with the falling timing of the data latch signal e.

On the other hand, the control signal @A+ is also supplied to the register update control circuit 7, so that the register update v1wJ circuit 7
From then on, the data wrap signal e is no longer extracted. Therefore, the data transfer operation of registers 41 to 43 is stopped, and the register value remains (N-+l). The 8 bits output from the registers 42 and 43 are supplied to the processor 5 via the data bus and read by the control fU numbers A2 and A3 based on address designation of the processor 5, respectively. At this time, since the register values (N+1) of the registers 41 to 43 remain, the processor +J5 divides and reads the counter values (N+1) of the registers 41 to 43.

Here, the pulse input is applied during this split read, and the counter value of counter 3 changes from (N13) to (N + 2).
Suppose that it is changed to . However, even if the value of the counter 3 is changed, the register values of the registers 41 to 43 remain as (N+1) due to the prohibition of the data latch 4n@e of the register update control circuit 7.
3, the register value (N+2) is never output. Therefore, as explained with reference to FIG. 4, even if the counter value is changed during divided reading, the processor will not read incorrectly, and can read the correct counter values for each of the 8 pits and b(N(l)).

Furthermore, in the present invention, the processor j5 reads the values of the registers 41 to 43 after the data transfer of the registers 41 to 43 is completed, that is, after the counter value has stabilized. There is no need to perform so-called "reading twice," the hardware load can be reduced compared to the conventional example, and programming can be simplified.

A flowchart of the processor 5 of the present invention is shown in FIG.

In step (2) in FIG. 3, data RA to RC are simply written from the registers to the memory in the processor 5 and stored as MA to MC, and the data are not compared as in the conventional case.

That is, when reading of the register 43 is completed, the control signal A
3, the inhibition of the data wrap signal e from the register update control circuit 7 is canceled, the counter value (N+2> is transferred to the registers 41 to 43, and the same operation as described above is repeated. In this case , the value of counter 3 is (N
+2) If the above split read is performed,
In the present invention, since "reading twice" is not performed, the counter value (N+2) immediately after the change can be read, and processing can be performed in a shorter time than in the conventional example.

Note that if the period of dividing read is longer than the period of changing the counter value, after dividing reading the counter value (N+1), reading the next counter value (N+3) without reading the counter value (N - 1-2). You'll end up paying a discount. This is used in a system that monitors changes at regular intervals, rather than monitoring the counter value each time it changes.

〔Effect of the invention〕

As explained above, according to the present invention, updating of the register value is prohibited while the processor is dividing and reading the register value, so even if the counter value is changed during the dividing read, the processor updates the register value before changing the counter value. It is possible to correctly divide and read the value of the counter without causing erroneous reading as in the conventional example. Also, since reading of the register value is started after register transfer is completed, stable counter values can be read, unlike in the conventional example. [Read twice, no need for step 1, this allows
The software load is relatively smaller than the conventional example, and the program's t! Only J-ri will suffice.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the present invention, Fig. 2 is an operation timing chart of the invention, Fig. 3 is a processor operation flowchart of the invention, and Fig. 4 is the state of the counter value! FIG. 5 is a timing chart when a counter value change occurs during a read period in split read. FIG. 6 is a conventional block diagram. FIG. 7 is a conventional processor operation flowchart 1-. In the figure, 1 is a pulse input terminal, 2 is a pulse synchronization circuit, 3 is a counter, 41 to 43 are registers, 5 is a processor, 6 is an address decoder, 7 is a register update control circuit, and 8 is a clock generator. Patent Applicant Fujitsu Ltd. Processor Operation Flow Chart of the Invention Figure 3

Claims (1)

[Claims] In a pulse counting device of a type in which a value (d) of a counter (3) whose value is changed every time a pulse is input is divided into a plurality of bit groups and read by a processor (5), the above-mentioned counter (3) and the processor (5),
A plurality of registers (4_1 to 4_3) provided corresponding to the number of the plurality of bit groups and a counter value (d) of the counter (3) are stored in the plurality of registers (4_1 to 4_3).
), the transfer timing of the registers (4_1 to 4_3) and the transfer timing to the counter (3) are adjusted so that the counter value (d) of the counter (3) does not change during the transfer of the registers (4_1 to 4_3). Counter input pulse (c)
A pulse synchronization circuit (2) that cycles the timing; and the processor (5) are connected to the plurality of registers (4_1 to 4_1).
During the period when the register value (f) of 4_3) is being read from the end of the register transfer, the above registers (4_1 to 4) are being read.
A pulse counting device comprising: a register update control circuit (7) that prohibits updating of register values in _3).