JPH0123730B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an ultrasonic flaw detection signal processing device, and in particular, to detect internal cracks and cavities occurring in physical properties in a non-destructive manner and process them as flaw detection signals by an electronic computer.

In a conventional system in which flaw detection signals from ultrasonic flaw detection are sent to an electronic computer and processed as information, the flaw detection signals received by the probe and amplified by the ultrasonic flaw detector are temporally detected within a set time range (gate range). A signal exceeding a certain threshold level is subjected to peak hold or sample hold, analog to digital conversion (hereinafter referred to as A/D conversion), and then sent to an electronic computer. The characteristics of ultrasonic waves are that they weaken in inverse proportion to the distance from the probe, and even for the same defect size, the level received changes depending on the distance. Similarly, forest-like echoes generated in the crystalline structure of the inspected material change depending on the distance, and therefore, when processing a signal that is twice as large as the forest-like echo as a defect signal, it is possible to It is not possible to distinguish the ratio (SN) between the forest echo and the defect signal using the same ratio. For this reason, some devices are equipped with an additional function that reduces the amount of amplification over time in the input signal amplification section of the flaw detector so that the display on the CRT display is a forest echo or defect signal that remains constant over changes in distance. . However, the amount of decrease over time in the amplifier itself is not displayed, making it unreliable, and it is necessary to create test materials for each product to measure the amount of decrease and guarantee the flaw detection results, and to check it at each step of flaw detection. It was hot.

In addition, since programming control using an electronic computer requires a certain amount of time, it is not possible to directly process signals obtained repeatedly from a flaw detector and digitized at supersonic speed, so a peak hold circuit is used as preprocessing. Alternatively, the maximum value within a certain period of time was used as information for the electronic computer using a digital comparison circuit. For this reason, a high-precision data processing system that receives and processes a plurality of defect signals using a single pulse signal requires a large, high-speed computer that can handle the processing speed. For this reason, the processing speed of the microcomputer could not process it, and only the largest signal among these multiple defects was processed. In such an apparatus, when defect information is obtained at a level that indicates a failure due to multiple defects, it is necessary to manually confirm the defective part again. Furthermore, when the received signal is directly A/D converted as described in Japanese Patent Publication No. 56-34060, the amount of data becomes enormous. In particular, for the purpose of processing defect signals that are twice the noise level or more, all noise echoes near the surface layer must be processed as signals. Also in the above publication, 50 μsec after receiving the defect signal.
The A/D conversion is performed only in the interval, but not over the entire area, which seems to be at the limit in terms of processing capacity.

In consideration of the above points, the present invention displays flaw detection signals on the same CRT display using a time-varying threshold level signal that can be adjusted manually or by a signal from a computer, and also displays these signals on the same CRT display. By making it possible to directly compare and extract only the defect signal, for example, a defect signal twice or more of the forest echo can be extracted without changing the original flaw detection signal. In addition, when multiple defective signals are received as one pulse signal and are A/D converted at supersonic speed and processed by a computer, the digital signal is temporarily converted to correspond to the processing speed of the computer. By storing it in FIFO memory, it is possible to process high-speed digital signals even at the processing speed of a microcomputer.

Furthermore, the speed of the received signal by ultrasonic flaw detection is
Since the flaw detection signal is a pulse signal, the interval between each pulse signal is 1/60 to 1/100 sec (16 msec to 10 msec). Also, in order to be able to handle multiple defects,
It is necessary to process data every 1 μsec. In this respect, by using a FIFO memory (FIFO buffer register or buffer memory for temporary storage), data processing can be performed between pulse signals (16 msec to 10 msec). Note that FIFO is a response to processing speed, and signals that are more than twice as large as forest echoes can be obtained by comparing the threshold level and the flaw detection signal. Figure 5 is an example signal diagram in this case.
a ₁ and a ₂ are pulse signals, b is a defect signal, c is a reception time of the defect signal of 0.5 msec, and d is a processing time without FIFO memory.

Thus, the present invention provides a threshold level signal and a gate range signal that change over time in response to a trigger signal generated based on a clock signal when processing an ultrasonic flaw detection signal via an electronic computer. a threshold circuit that generates the flaw detection signal and the threshold level signal, a comparison circuit that extracts only the defect signal given the flaw detection signal and the threshold level signal, a sample hold circuit and an A/D conversion circuit that digitize the defect signal, and the digitization circuit. a first FIFO memory for temporarily storing a defective signal;
a counter circuit to which the start and end signals of the gate range signal and the clock signal are sent to count the number of clocks; a matching circuit which extracts the counter amount of the clock signal and extracts it as a distance signal by matching with the defect signal; and the distance signal. and a second FIFO memory that temporarily stores the
The device is characterized in that data analysis processing is performed on these stored signals based on a program built into the CPU, and the results are stored in the main memory. Thus, according to the present invention, the aforementioned Japanese Patent Publication No. 56-
Unlike Publication No. 34060, when it is necessary to process a maximum distance of 1μ500mm, a huge amount of memory and ultra-high-speed processing are required, which is practically impossible, but the amount of data is reduced using an analog comparison circuit. This allows processing to be performed without limiting the range of A/D conversion.

The present invention will be explained with reference to the embodiment shown in the figure.
FIG. 1 is a block diagram of an ultrasonic flaw detection processing apparatus. In the figure, 1 is the probe, 2 is the ultrasonic flaw detector, and 3
is a clock circuit, 4 is a trigger circuit, 5 is a threshold circuit, 6 is a comparison circuit, 7 is a sample hold circuit, 8 is an A/D conversion circuit, 9 is a first
FIFO memory, 10 is a counter circuit, 11 is a coincidence circuit, and 12 is a second FIFO memory.

For other items belonging to electronic computers, 13 is
A CPU, 14 is a memory, or an input/output controller, an arithmetic controller, etc. (not shown), and 15 is a bus line, which includes, for example, a 16-bit data bus, a 17-bit address bus, and a 2-bit control bus. shall consist of. Next, the operation will be explained with reference to FIG.

First, the CPU 13 provides a start signal to the clock circuit 3, thereby generating a clock signal in the clock circuit 3, and based on this, the clock signal is provided to the trigger circuit 4 to generate a trigger signal. By applying this trigger signal to the ultrasonic flaw detector 2, an ultrasonic wave is generated as a pulse signal from the probe 1 toward the object to be inspected. It is included as a flaw detection signal in the reflected wave from the flaw detector 1 to the flaw detector 2 and is extracted. On the other hand, the threshold circuit 5 receives the trigger signal from the trigger circuit 4 and generates a threshold level signal and gate signal that change over time, which are sent to the flaw detector 2 and displayed on the CRT display of the flaw detector 2 as a flaw detection signal. be done. Further, the flaw detection signal from the flaw detector 2, the threshold level signal and the gate range signal generated by the threshold circuit 5, that is, the gate start signal and end signal, are sent to the comparison circuit 6, and only the defect signal is extracted. Since this defect signal is an analog signal, it is taken out as a digitized voltage level signal by the sample and hold circuit 7 and the A/D converter circuit 8, and is temporarily stored in the first FIFO memory 9. Further, the clock signal from the clock circuit is sent to the counter circuit 10 in response to the gate range start signal from the threshold circuit, and the number of clocks begins to be counted, and is counted out in response to the end signal. The counter value from the counter circuit 10 and the defect signal from the comparator circuit 6 are given to the matching circuit 11, and this count number is converted into a distance signal, that is, the ultrasonic wave from the probe 1 is reflected by a crack or the like and received by the flaw detector 2. The signal is extracted as a time signal until the signal is reached, and is temporarily stored in the second FIFO memory 12. Note that since this distance signal is processed by the counter circuit 10, the numerical processing is already digital and an A/D converter is unnecessary. These first and second
The signals stored in the FIFO memories 9 and 12 undergo data decomposition processing based on a program built into the CPU, and the results are stored in the main memory 14 and can be read out as needed.

Incidentally, FIG. 2 is a flaw detection line diagram at the conventional threshold level, FIG. 3 is a flaw detection line diagram using the same distance amplitude correction circuit, and FIG. 4 is a flaw detection line diagram according to the present invention. As an example, the trigger signal is 60 to 250 Hz, the sample hold is 50 μsec, the defect signal is sampled, the maximum differential pressure between them is extracted by continuously quantizing for 1 μsec, and the differential pressure extracted by the sample hold circuit is is digitized into a 28-bit value in 450 μsec using an analog-to-digital converter.

As explained above, the present invention is capable of extracting a signal that is more than twice as large as the forest echo without changing the flaw detection signal, and further, that a microcomputer can process the repeatedly generated high-speed digitized signal. As a result, it has become impossible to obtain highly reliable ultrasonic flaw detection signals using inexpensive systems.

[Brief explanation of drawings]

The drawings show an embodiment of the ultrasonic flaw detection signal processing device of the present invention. Fig. 1 is a block diagram, Fig. 2 is a flaw detection line diagram at the conventional threshold level, and Fig. 3 is a flaw detection using the same distance amplitude correction circuit. FIG. 4 is a flaw detection line diagram according to the present invention, and FIG. 5 is a signal example line diagram for explanation. In the figure, 1 is a probe, 2 is an ultrasonic flaw detector, 3 is a clock generation circuit, 4 is a trigger circuit, 5 is a threshold level generation circuit, 6 is a comparison circuit, 7 is a sample hold circuit, and 8 is an analog/digital circuit. A conversion circuit, 9 a first FIFO memory, 10 a counter section, 11 a coincidence circuit, 12 a second FIFO memory, 13 a CPU, and 14 a memory.

Claims (1)

[Claims] 1. When processing ultrasonic flaw detection signals via an electronic computer, a threshold that generates a threshold level signal and a gate range signal that change over time in response to a trigger signal generated based on a clock signal. a comparison circuit that receives the flaw detection signal and the threshold level signal and extracts only the defect signal; a sample-hold circuit and an A/D conversion circuit that digitizes the defect signal; A first FIFO memory for temporary storage, a counter circuit to which the start and end signals of the gate range signal and the clock signal are sent to count the number of clocks, and a counter circuit that takes out the counter amount of the clock signal and matches it with the defect signal. It is equipped with a matching circuit that extracts the distance signal as a distance signal and a second FIFO memory that temporarily stores the distance signal, and analyzes the stored signals based on a program built into the CPU. An ultrasonic flaw detection signal processing device characterized in that results are stored in main memory.