JPH01237990A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To make unnecessary the serial-parallel conversion of input output data and to miniaturize a device by controlling the data transfer by an internal address in units of a block equivalent to a memory capacity and making preparations for the clear mode of the internal address. CONSTITUTION:A control circuit 116 temporarily accumulates input data Din to writing data register WDR 103 or 104, designates by the serial address generated internally automatically in units of the block equivalent to the memory capacity of WDR and transfers to a memory cell array 1 or 2. In the same way, a control circuit 117 designates the data in an array 1 or 2 by the serial address of the internal generation in units of the block equivalent to the memory capacity to reading data register RDR 108 or 109, transfers from the array 1 or 2 into RDR 108 or 109, and reads them as output data Dout. Two types of the action mode to clear the internal address to a peak address are prepared, and one side mode, at the time of clearing, executes the transfer from the WDR to the array and executes the transfer from the array to the RDR and other side mode does not execute respective transfers.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor memory, and particularly to a semiconductor memory that can obtain a data delay corresponding to one field or one frame of a television signal, and that can initialize an internally generated address to the first address. The present invention relates to a semiconductor memory characterized by having two types of operation modes upon (resetting).

[Conventional technology]

Conventionally, a general-purpose dynamic RAM has been used to delay data corresponding to one field or one frame of a television signal. When digitally processing radio waves sent using the NTSC system, which is the broadcasting system of the United States and Japan, the number of samplings is determined by considering the band of the video signal to be processed, but the ease of data processing is advantageous. Therefore, the color signal subcarrier (f S C#3.58M
A zumbling frequency of four times Hz) is often used.

That is 3.58MHz x 4# 14.3MHz
Sampling is performed and processed in (1 cycle 70 ns).

In this case, one horizontal scanning line (line) of the television signal
The number of samples per field is 910.1 fields (26
The number of samplings per line (2 to 263) is 910X
262 (263)=238420 (239330), and the number of samples per frame (525 lines) is 910×525=477750. Further, the number of pixel gradations per sampling point is approximately 8 bits. Therefore, when sampling at 14.3MHz, to obtain one frame of data delay, 477
A memory element of 750 x 8 bits or more was required. FIG. 2 shows a circuit when this memory is constructed from a conventional general-purpose memory. That is, five general-purpose memories each having a 128K x 8 bit configuration were used to form a 128K x 40 bit configuration, and data was written and read at the same address in units of 40 bits by read-modify-write cycles. One frame consists of 477,750 x 8 bits, but when handling data in units of 40 bits, there are 955
The address generator generates an address starting from address 1, and when it reaches address 95550, the next address is controlled to be address 1 again. Input/output data is written/written to memory in 40-bit units.
Since reading is performed, the input data is 8 bits → 40 bits input data serial/parallel converter, and the output data is 40 bits.
Bit→8 bit output data is accessed through a parallel to serial converter. Also, one cycle of input data and output data is 70 ns, but since 5 cycles are written/read to the memory at once, the memory read/modify write cycle time is 70 n 5X5 = 350 ns.
Therefore, it can be done easily.

[Problem to be solved by the invention]

Since the conventional circuit described above uses general-purpose memory, it requires a serial/0 parallel converter for input/output data, and an address generator adjusted to obtain a data delay of exactly one frame. There are disadvantages in that many accessory parts are required and the device becomes larger.

[Means to solve the problem]

The semiconductor memory according to the present invention temporarily stores write data from a data input terminal in a write data register, and stores the write data in blocks corresponding to the memory capacity of the write data register in memory designated by a serial address that is automatically generated internally. A read data register is provided that specifies the means for transferring and writing data to the cell and the data stored in the memory cell using an internally automatically generated serial address, in block units corresponding to the memory Jft of the read data register. A FIpo-like semiconductor memory that has a means for reading read data from a read data register through a data output terminal, and that can obtain a data delay of one field or one frame, and this memory is When initializing an address, the data previously stored in the write data register is transferred to the address specified by the internal address, and the read data corresponding to the initialized first address is transferred to the read data register. There are provided means for resetting the internal address to the first address without any operation, and means for resetting the internal address to the first address without performing these transfer operations.

In contrast to the conventional one-field or one-frame delay circuit for television signals, etc. using the conventional general-purpose DRAM described above, the image memory of the present invention has a means for writing white data into the memory and a means for reading read data from the memory. By improving this and adding a means to reset the internally generated address to the initial address (first number) in two different modes, it is possible to achieve extremely simple control and initialize (reset) the memory according to the situation. , it has the original content of being able to construct a one-field or one-frame delay circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor image memory showing an embodiment of the present invention.

101.102 is the write data register 103゜10
A column address generated from the write address generator 112 is decoded by a column decoder for selecting write address No. 4. 103 and 104 are write data registers, and write data from the data input terminal Din is temporarily stored and accumulated in these registers. 106 and 107 are m columns ρ
A memory cell array 1 has a column configuration, and a memory cell array 2 has a configuration of m rows and p' columns. 105 is a row decoder for selecting a row of memory cell array 1 and memory cell array 2; 108 and 109 are read data registers for temporarily storing and accumulating read data from the memory cell array 1 and the memory cell array 2.

Column decoders 110 and 111 select a read address on the read data register, and decode the column address from the read address generator 113. 11
2 is a write address generator that generates a column address and a row address for writing. This circuit can be constructed from a counter for generating column addresses and a counter for generating row addresses.

A read address generator 113 generates a column address and a row address for reading. This circuit can also be constructed from a counter for generating column addresses and a counter for generating row addresses. Reference numeral 114 denotes a refresh address generator, which is required when memory cell arrays 1 and 2 are configured with dynamic memories. This circuit is composed of a refresh timer and a counter for generating refresh addresses. 115 is a multiplexer for switching the write row address, read row address, and refresh address. 116 is a write control circuit which sends the write lock signal WCK and the data being written to the write data register 103 or 104 to the memory cell array 10.
6 or 107, the write address of the write address generator 112 is initialized (starting address).
The write address of the write address generator 112 is set to the initial value (starting address) without the clear signal WCLR and the operation of transferring the unwritten data to the write data register 103 or 104 to the memory cell array 106 or 107. Clear signal WCL to return
It inputs RI and generates an address reset signal, a data transfer control signal from the write data register to the memory cell array, etc.

117 is a read control circuit, which outputs a read clock signal RC.
Clear signal RCLR and memory for returning the read address of the read address generator 113 to its initial value (first address) without the operation of transferring K and the data in the first row of the memory cell array 106 or 107 to the read data register 108 or 109. Cell array 106 or 10
The read address of the read address generator 113 is set to the initial value (first address) without the operation of transferring the data in the first row of 7 to the read data register 108 or 109.
It inputs a clear signal RCLRI to restore the original state, and generates an address reset signal and a data transfer control signal from the memory cell array to the read data register.

Next, the operation of the semiconductor memory configured in this manner will be explained.

Writing begins with clear signal WCLR or WCLRI.
The write address generator is cleared by the signal, and both the write column address and row address are reset to the leading address. If the WCLR signal is input at this time, the data in the write data register specified by the column address set at that time is transferred to the memory cell array corresponding to the address specified by the write row address, and then the address is changed. Since it is reset, the time required for this data transfer is required as a clearing period.

In this case, although the time required for clearing is relatively long, there is an advantage that, for example, data previously written in the write data register is transferred and stored within the memory cell. Further, when the WCLRI signal is input, since no transfer operation is involved, the data previously written to the write data register is not stored in the memory cell, but there is an advantage that the clearing period can be made very short. When clearing is completed, the column address is incremented in synchronization with the WCK signal, and Din
Data input from the terminal is accumulated in the write data register. Immediately after clearing, the write data register 103 is selected, so data is stored in the write data register 103 first.

When writing is performed ρ times, the write data register 10
3 becomes full, and data is subsequently stored in the write data register 104. At this time, the light control circuit 116
detects that the write data register 103 is full and generates a control signal to transfer the data in the write data register 103 to the first row (first row) of the memory cell array 1 all at once. Write data register 1
When data starts to be stored in 04 and is written β' times, the write control circuit writes data to write data register 1.
04 data is collectively stored in the first row of memory cell array 2 (
At the same time, the write column address returns to address 1, and the data from the Din terminal is stored in the write data register 103 again in synchronization with the write clock WCK.

Note that when the write column address returns to address 1, the write row address is incremented by one address, so the newly stored data in the write data registers 103 and 104 is stored in the memory cell array 1. ．． The data is transferred and stored in the row of memory cell array 2. Similarly, the contents of the write data register are transferred to addresses incremented sequentially from the third row to the fourth row, and when the last row is reached, the data transfer of the write data register is repeated again from the first row.

Next, for reading, first use the clear signal RCLR or RCLR.
The read address generator 113 is cleared by the 1 signal, and both the read column address and row address start address (
address 1). If the RCLR signal is input at this time, the read column and row address is set to address 1, and at the same time, the data of the row to be read first, that is, the data of the first row of the memory cell array 1, is stored in the read data register 108 all at once. Since the data is transferred, the time required for this transfer is required as a clearing period. In this case, the time required for clearing is relatively long, but there is an advantage that the data to be read out as the data of the first row and to be 2 is transferred and secured in advance to the read data register.

In addition, when the RCLRI signal is input, since no transfer operation is involved, the data that should be read as the first row data is not secured in the read data register, and accurate data cannot be read, but the clearing period is very short. It has the advantage of being able to do this. When clearing is completed, the column address for reading is set to address 1, but thereafter the column address is incremented in synchronization with the RCK signal, and reading from the read data register 108 is performed in accordance with each address.

Note that when resetting is performed using RCLRI, the data in the first row is not transferred in advance, so the data that has been stored in the read data register 108 up to that point is read out. Note that when clearing is executed, the data of the next row to be read, that is, the data of the first row of the memory cell array 2, is transferred to the read data register 10 at the same time as data reading is started.
9 is automatically transferred. At this time, when the data in the first row of the memory cell array 2 is completely transferred to the read data register 109, the row address for reading is incremented by one address. Therefore, when reading is completed ρ times from the read data register 108 after clearing, reading from the read data register 109 is started, and at the same time, the data in the second row of the memory cell array 1 is transferred to the read data register 108 at once by the read control circuit. be transferred. Also, read data register 109
After p' readings are performed from memory cell array 2
After the second row of data is transferred to the read data register 109, the read row address is incremented by one. Similarly, when reading from the read data register is completed, data is transferred from the third and fourth rows of the memory cell array, sequentially incrementing addresses, and when the last row is reached, the read data is transferred again from the first row. Transfers are configured to repeat. Here, how to use the clear signals WCLR, π and ■π and WCLRl and RCLRl will be explained in more detail.

This memory is connected to one frame of data delay line, e.g.
Taking C method 4fsc sampling as an example, the number of pixels in one scanning line is 910 pixels, and the number of scanning lines is 5.
There are 25 lines, so in Figure 1, ρ+' = 910 address Xn (n corresponds to the number of gradations, for example 8) and m = 525
Ideally, this would be the case. When this memory is used as a delay line corresponding to one frame adjustment, the following procedure is performed. WCK and RCK are commonly connected and input the same clock signal. In WCLR, π, ■π is connected in common, and W
CLRl and RCLRl are also commonly connected.

By inputting a clear signal to either WCLR, RCLR or WCLRl, RCLRl, the write/read address is cleared to the first address, and writing of write data and reading of read data are performed in the write data register;
This is done for the read data register. On this occasion,
The transfer of write data to the memory cell is performed after the write data register is full, so when the write and read addresses are the same, the read data is data delayed by exactly the amount of pixels corresponding to all addresses of this memory, that is, 910X525. Data delayed by =477750 pixels is obtained. Next, set this memory to 1
Consider the case where it is used as a data delay line corresponding to a field. i.e. 910X262 (or 263)
=238420 (or 239330) When used as a pixel delay line, adjust with a clear signal.

Here, when controlling using WCLR and RCLR, a relatively long clearing time is required because a transfer operation is involved.
For example, if this clearing time is 1 μS, the clearing time will be approximately 15 cycles (1000ns/70ns#1
Since the clock corresponding to 5) is input, the number of delay cycles to input the clear signal is 238420-15=23.
8405 (or 239330-15=23931
You will need to enter the information in step 5). In this case, memory control is a little complicated, but 262 (or 2
63) There is an advantage that unwritten data in a row and read data in the first row can be secured. On the contrary, WCLRI
, RCLRI does not involve a transfer operation, so the clearing time can be made very short and, for example, it is possible to initialize the internal '7 address counter to the leading address in one cycle (70 ns). In this case, there is an advantage that memory control of the delay length becomes very simple. In this case, the read data to be displayed in the first line is 262
(or 263) row is not secured, but this part often does not contain video signals during the vertical synchronization period or field switching, so accurate reading does not need to be performed. There are many cases where there is no problem. Finally, a case will be described in which data transfer from the write data register to the memory cell and transfer and refresh of the read data register l\ from the memory cell are requested simultaneously in this memory. In this case, although not shown, an access order arbitration circuit (arbitration circuit) is provided, so that even if three requests are made at the same time, they can be performed one by one in an orderly manner. Even if a transfer request for the write data register and read data register occurs, access from the Din and Dout terminals is performed from the other register, so writing or reading will not be interrupted.

- Strategically, this data transfer or refresh period ends in about 300 ns. On the other hand, p+ρ'=910
When addressing, the access period for one register is approximately 32 μs (70 ns x 455L; 32 μS), so data transfer from write data register to memory cell, data transfer from memory cell to read data register, and refresh are performed during 32 μs. There is no problem in ending it.

〔Effect of the invention〕

As explained above, according to the present invention, input data is temporarily stored in a write data register, and means for transferring it to a memory cell by specifying it by a serial address automatically generated internally in blocks corresponding to the memory capacity of the write data register; Similarly, the accumulated data in the memory cell is transferred from the memory cell to the read data register by specifying it using an internally automatically generated serial address in block units corresponding to the memory capacity of the read data register, and read from there as output data. There are two types of operation modes for clearing the internal address to the first address.
One is an operation that involves data transfer from the write data register to the memory cell and from the memory cell to the read data register when cleared, and the other is an operation that does not involve these transfers. By doing so, it can be used as a data delay line of a fixed size corresponding to the built-in memory capacity, and also allows a data delay line of any size by using a clear signal. However, it has the advantage that it is possible to select a means that can secure read data and perform reset.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention. FIG. 2 shows an example of the configuration of a one-frame delay circuit using a conventional general-purpose memory. 101.102・・・Column decoder for write,
103.104...Write data register, 1
05...Routeco-y, 106,107...
...Memory cell array 1 and 2.108,109...
...Read data register, 110, 111...
... Read column decoder, 112 ... Write address generator, 113 ... Read address generator, 114 ... Refresh address generator, 115 ...・Address switching multiplexer, 116...Write control circuit, 117...
...Read control circuit, WCK, RCK...Write clock, read clock, WCLR. RCLR...Write address clear signal, read address clear signal, WCLRl, RCLRl...
...Write address clear 1 signal, read address clear 1 signal, 21...Serial-to-parallel conversion circuit, 22.
...Parallel-serial conversion circuit, 23...128K
128 x 40 bit configuration memory system using 5 x 8 bit general purpose memories, 24...address generator. Agent Patent Attorney Oto Uchihara

Claims (1)

[Claims] The write data from the data input terminal is temporarily stored in the write data register, and is transferred in blocks corresponding to the memory capacity of the write data register to the memory cell specified by the internally automatically generated serial address. The data stored in the memory cells is specified by an internally automatically generated serial address and transferred to the read data register in block units corresponding to the memory capacity of the read data register. In a FIFO type semiconductor memory having a means for reading read data from a read data register via a data output terminal and obtaining a data delay of a pixel equivalent to one field or one frame of a television signal, the write This involves the operation of transferring the data stored in the data register to the specified memory cell, or the operation of transferring the contents of the specified memory cell to the read data register, and converts the internal address to the initial address (starting address). Internal initial address without means for resetting and an operation of transferring the data stored in the write data register to the specified memory cell or an operation of transferring the contents of the specified memory cell to the read data register. A FIFO type semiconductor memory characterized in that it is provided with means for resetting.