JPH0123979B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention uses a split-phase code as a code format and generates a bit synchronized clock used when sampling demodulated data in a data transmission system receiving circuit that performs FSK modulation. Regarding equipment, its clock is accurate and
The purpose is to make it easily obtainable.

A conventional bit synchronous clock generator will be explained. In Fig. 1, 1 is an FSK demodulator;
2 is a bit change point detection circuit, 3 is a bit synchronized clock generation counter, and 4 is an oscillation circuit.

FIG. 2 shows the signal waveforms of the main parts in FIG. 1, where A is the FSK modulation signal, B is the demodulation signal, C is the bit change point signal, D is the oscillation clock, and E is the bit synchronization clock.

In the device configured in this way, the FSK modulated signal A is demodulated by the FSK demodulator 1.
The bit change point detection circuit 2 detects the bit change point of the demodulated signal (B), generates the bit change point signal (C), resets the bit synchronized clock generation counter 3, and corrects the bit synchronized clock. There is. Note that the frequency division of the bit synchronous clock generation counter 3 is set to N, and the output clock number is set to N.
t _O , and if the data transmission rate of the received signal is T _O , then t _O
＝NT _O condition must be met.

However, in this configuration, t _O =
Since a high-precision oscillation circuit 4 that satisfies the _NTO conditions is required, the receiving circuit has the disadvantage of being expensive and complicated.

The present invention solves these drawbacks and will be described below along with examples thereof.

In FIG. 3, 5 is an FSK demodulator, 6 is a counter that operates only in the case of a mark signal, 7 is a counter that operates only in the case of a space signal, 8 is an OR circuit, and 9 is a binary counter.

Figure 4 shows the signal waveform of the main part, where a is
FSK modulation signal, b is a demodulation signal, c is a clock signal generated in response to a mark signal, d is a clock signal generated in response to a space signal,
e is an OR signal of clocks c and d generated in response to mark and space signals, and f is a bit synchronization clock.

Next, the operation of this embodiment will be explained. The input FSK modulated signal a is demodulated by the FSK demodulator 5. Depending on the mark and space states of the demodulated signal b demodulated in this way, the counter 6
Select one of 7, divide the FSK modulation signal,
It generates signals c and d that are the basis of the bit synchronized clock. The counters 6 and 7 are configured to count 1/f ₁ and 1/f ₂ , respectively, where f ₁ and f ₂ are the frequencies of the mark and space states of the FSK modulated signal. Therefore, the 1/f ₁ counter 6 operates in the mark state, and the 1/f ₂ counter 7 operates in the space state, generating the clocks indicated by c and d. Note that the counters 6 and 7 do not operate continuously for one data length or more because the demodulated signal is a split phase code. Further, as shown in the figure, the signal e generated by ORing clocks c and d corresponds to a split phase code, so it is a clock signal with a speed twice as high as one data length. Therefore, by dividing the signal e by a binary counter, a bit synchronized clock f corresponding to one data length can be obtained.

As is clear from the above examples, according to the present invention
Since the bit-synchronized clock can be obtained directly from the FSK modulated signal, an oscillation circuit for generating the bit-synchronized clock in the demodulation section is not required, and even when the FSK modulated signal is recorded on tape or the like and played back. It has features such as being able to reproduce a bit synchronized clock while following fluctuations in tape speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional bit synchronous clock generator, FIG. 2 is a timing chart of the same, FIG. 3 is a block diagram of a bit synchronous clock generator according to an embodiment of the present invention, and FIG. 4 is a timing chart of the same. It is. 5...FSK demodulation section, 6, 7...Counter, 8
...OR circuit, 9...binary counter.

Claims (1)

[Claims] 1. An FSK demodulator that demodulates a carrier signal that has been FSK-modulated using a split-phase code; a mark counter that receives the carrier signal and operates only in the case of a mark signal; and a mark counter that receives the carrier signal and operates only for mark signals; A bit synchronous clock comprising: a space counter which operates only when the mark counter is set; an OR circuit which takes the logical sum of the space counter and the mark counter; and a binary counter which inputs the output of the OR circuit and outputs a bit synchronous clock signal. Generator.