JPH01241645A - Arithmetic processing unit - Google Patents

Abstract

PURPOSE:To attain the high speed access of a cache memory by directly connecting between the cache memory and an LSI chip with a chip having cross bar switch function in a data bus for the reading/writing of the cache memory. CONSTITUTION:Cache memories 83 and 84 are divided into >=2 banks and the cache memories 83 and 84 and more than 2 LSI chips are connected through the chip to have a cross bar switch 70 which can obtain a connecting condition between arbitrary input and output terminals. Then, data is transferred simultaneously through the chip having the cross bar switch 70 between the >=2 different LSI chips and the >=2 different banks of the cache memories 83 and 84. Thus, through the chip having the cross bar switch 70, the data is transferred simultaneously between the divided banks of the cache memories 83 and 84 and the different LSI chips. Thus, the efficiency of the data transfer can be improved.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an arithmetic processing unit that constitutes a part of an information processing device, and in particular to a cache in an arithmetic processing unit that is composed of a cache memory and a plurality of LSI chips. -Relates to technology related to data transfer between memory and LSI chips.

[Conventional technology]

In recent years, there has been remarkable progress in the integration of electronic devices, and high-performance arithmetic processing units have come to be realized using several LSI chips.

Incidentally, such high-performance arithmetic processing devices employ cache memory for the purpose of further speeding up processing, but when there are multiple LSI chips, cache memory
The memory output destination and write source will span multiple LSI chips, and if each data path is provided, the number of cache memory pins will become enormous. Therefore, a data path is not provided for -S. It is made into a path and used commonly by each LSI chip, so that the number of pins is within the limit.

[Problem to be solved by the invention]

As mentioned above, conventional arithmetic processing units have a cache
The number of pins in the cache memory was reduced by making the data node for accessing the memory a bus. However, as the number of LSI chips connected to the bus increases, the line length of the bus becomes longer, and the delay time of signals on the bus increases due to the increase in capacitance, making it impossible to access the cache memory at high speed. .

■Since it is a bus method, only one data transfer is possible in one cycle.

There were other drawbacks.

In particular, in arithmetic processing units that pipeline cache memory accesses, an increase in cache memory read time is a direct factor that hinders shortening of machine cycles. Therefore, countermeasures for (2) were an important issue. In addition, (2) was also an important problem in improving the efficiency of data transfer.

The present invention has been proposed in view of the above points, and its purpose is to enable high-speed cache memory access and to improve the efficiency of data transfer by enabling two or more data transfers at the same time. The object of the present invention is to provide an arithmetic processing device that can increase the performance.

(Means for Solving the Problems) In order to achieve the above object, the present invention includes a cache memory and a plurality of LSI chips, and the present invention includes a cache memory and a plurality of LSI chips. In the arithmetic processing unit where the transfer is performed, the cache memory is divided into two or more banks, and the data is transferred via a chip having a cross bar switch function that can connect arbitrary input/output terminals. The cache memory and two or more of the LSI chips are connected through the chi knob having the cross bar switch function.
Data transfer is simultaneously performed between two or more different LSI chips and two or more different banks of the cache memory.

[Effect]

In the arithmetic processing device of the present invention, data is simultaneously transferred between divided banks of the cache memory and different LSI chips via a chip having a cross bar switch function.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a configuration diagram showing an embodiment of an information processing device including an arithmetic processing device of the present invention. In FIG. 1, reference numeral 90 is an arithmetic processing unit to which the present invention is applied, and this arithmetic processing unit 90 is connected via a system bus 94 to a main memory 91.
Input/output control device 92° is connected to system control device 93. Although not shown in FIG. 1, in a multiprocessor configuration, several other arithmetic processing units may be connected to the system bus 94, and when the main memory capacity is increased, multiple main memory devices may be connected to the system bus 94. It is connected to bus 94.

The arithmetic processing unit 90 also includes an instruction control circuit 10.address conversion control circuit 20. Bus control circuit 30° arithmetic control circuit 40. High-speed arithmetic circuit 50. Each LSI chip constituting the control memory circuit 60, a control memory 85 composed of a plurality of random access memories (RAM), cache memories 83 and 84, and an address array (AA).
81, a copy address array (CAA) 82, and a cross bar consisting of multiple LSI chips.
It is composed of a switch 70.

Next, read operations for the cache memories 83 and 84 and the main storage device 91 will be described. First, an instruction or operand read instruction and a read address are transferred from the instruction control circuit 10 to the address conversion control circuit 20 via the connection 102. If the above read address is a virtual address, address conversion control circuit 2
0, the virtual address is converted to a real address. The address conversion control circuit 20 connects the read real address to the wire 201
．． 202, 203, and 204, and stores the correspondence between the cache memories 83 and 84 and the main memory bag rf191, that is, the registration information of the cache memories 83 and 84, and determines the presence or absence of registration from the address array 81. It is determined whether or not there is a cache hit (registered) based on the signal sent back via the connection 202°, and if it is a cache hit, the read data of the cache memory 83 or cache memory 84 is validated and the cross bar switch is activated. The data is sent back to the read destination LSI chip via 70. - For boat fishing, the return destination is the instruction control circuit 10 in the case of command reading, and the arithmetic control circuit 40 in the case of operand reading, but in special operations, it is sent to the address conversion control circuit 20 or the high-speed arithmetic circuit. It can even be 50.

On the other hand, if there is no cache hit (called a cache miss or NFB), the bus control circuit 30
A block transfer request is sent to the main storage device 91 via the system bus 94. And the main storage device 9
After passing through the bus control circuit 30, the data returned from the connection 307.1 passes through the bus control circuit 30. Cross bar switch 70. Connection 83
7 or connection 847 to cache memory 83 or cache memory 84. Further, the first return data from the main memory @j2n91 is returned from the cross bar switch 70 to the return destination, and a successive operation is executed as 0 or more.

Next, write operations to the cache memories 83 and 84 and the main storage device 91 will be explained. First, the write instruction and write address require a write operation in the instruction control circuit 10! It is created in the instruction control circuit 10 when an instruction for . If the write address is a virtual address, it is converted into a real address by the address conversion control circuit 20, and then held in a register that holds the write address in the address conversion control circuit 20, and the write data is processed by the high-speed arithmetic circuit 50 or the like. At the time of preparation, writing to the cache memory 83 or the internal storage memory 84, and sending a write instruction to the main storage device 91, a write address, and write data to the bus control circuit 30 are executed.

However, cache memory 83 or cache °
Writing to memory 84 is performed only when the relevant address is registered in cache memory 83 or cache memory 84.

Then, the bus control circuit 30 executes writing to the main memory device 91 via the system bus 94.

Note that the write data is prepared in the arithmetic control circuit 40 mainly under the control of the micro program, and after being sent via the connection 405 to the register that holds the write data in the high-speed arithmetic circuit 5o, it is synchronized with the write address. and connect it to the cross bar swift 7 via NlA307.
0 and is transferred to the bus control circuit 30 and cache memory 83 or cache memory 84.
A write operation is executed as described above.

Data read and write operations for the cache memories 83 and 84 and the main storage device 91 are executed as described above, but the data lines through which data is transferred all constitute each circuit as shown in the figure. It is arranged so that LSI chips are connected one-to-one, and connections other than those selected by the cross bar switch 70 are not affected, and the line length of the access bus is minimized. Since each LSI chip can be mounted on the puff cage, it is possible to significantly reduce the delay time caused by the data lines on the puff cage. That is, when applying the conventional device to the embodiment shown in FIG.
7,307,837.847 were connected in parallel, which increased the total line length, increased capacitance, and increased delay time during data transfer. According to the present invention, only the capacitance of the connection selected by the cross bar switch 70 is involved, and the access bus can be the shortest, so the delay time caused by capacitance can be significantly reduced. This means that it can be shortened to .

Next, FIG. 2 is a configuration diagram showing an example of the internal configuration of the cross bar switch 70 in FIG. 1.

In Figure 2, 847, 837, 307, 207・
507, 407, and 107 are cache memories 84. and 107, respectively, as shown in FIG. Cache memory 83. Bus control circuit 30. Address conversion control circuit 20.
High-speed arithmetic circuit 50. Arithmetic control circuit 40. Command control circuit 1
This is the connection connected to 0. Note that although they are simplified in the figure (the connections 847, 837, 307, 207
, 507.107 have a data width of, for example, 8 bytes (64 bits).However, only the connection 407 has a data width that is different from the others, and is, for example, 4 bytes. Therefore, the conclusion vA847,837°307.207
．． Selectors 710 to 716 and input/output drivers are provided corresponding to 507, 407, and 107, respectively, and connection 2, which is the cross bar switch 700 control line, is provided.
Select signal 20 of selectors 710 to 716 as 05
5-30 to 205-36 and driver output enable signals 205-EO to 205-E4 are applied to the individual selectors 710 to 71 by the address conversion control circuit 20.
For example, when reading data from the cache memory 83 to the instruction control circuit 10, the selector 716 controls the connection 107.
and connection 837.

Although it is not the direct content of the present invention, this cross
The bar switch 70 also has the function of converting the data width, and can connect LSI chips with non-uniform data widths. The data width is different from the others, for example, 4 bytes.) When accessing the cache, selector 7 is used.
15 is connection 837 or connection 8 depending on the read address.
The uni select signal 205- selects 47 input data and further selects either the upper 4 bytes or the lower 4 bytes within the 8 bytes according to the read address.
By providing 35, 8-byte data can be returned to the arithmetic control circuit 40 as 4-byte data. Note that other LSI chips, such as the instruction control circuit 10
When reading data to, the data width of connection 107 is 8 bytes, which is the same as cache memory 83, 84, etc.
There is no need to select 4-byte units.

Next, FIG. 3 shows the address conversion control circuit 2 in FIG.
This shows a part of the internal configuration of 0.

In FIG. 3, the request code is a code containing information that instructs a continuation operation or a write operation given from the instruction control circuit 10, and the request address is a read or write address given from the instruction control circuit 10. (If the read/write address given from the instruction control circuit 10 is a virtual address, it is after the real address has been converted).

The operation will be explained below. First, when a request code and a request address are given to connection &'J20-101 and connection 20-201, the request code is stored in request code register 2.
0-10, and the requested address is set in the real address registers 20-20.0 In normal conditions, when a request is accepted, the requested address is written in the real address registers 20-20, and at the same time, the requested address is set in the AA address register 20.
-30 and a part of the requested address is also sent to the DA address registers 20-40 or 20-41. During a read or write operation, AA address registers 20-30. DA address register 20-40゜20-41 to connection 202~
Addresses are given to address array 81 and cache memory 83 or cache memory 84.
is read out and checked in address array 81 to see if it is a cache hint. In the case of a read operation, if it is a cache hint, the data read from cache memory 83 or cache memory 84 is returned to the read destination via cross bar switch 70. Note that whether the read data is returned from the cache memory 83 or the cache memory 84 is determined according to the value of a predetermined 1 bit in the request address, and when the value of this bit is "0", the read data is returned from the cache memory 83 or the cache memory 84.
Memory 83 (bank #0) is selected, and when it is "1", cache memory 84 (bank #1) is selected. On the other hand, if it is not a cache hint (cache
In the case of a miss), the address for block transfer to the main memory bag W191 is sent from the real address register 20-20 via the selector 20-23 to the bus control circuit 30 via the connection 201, and the block read out by the bus control circuit 30 is sent. When the transferred data is returned for the first time, the data is
The data is sent back to the reading destination via the bar switch 70 and simultaneously registered in the cache memory 83 or cache memory 84. Note that, assuming that the block size is 32 bytes and the data transfer width is 8 bytes, the block transfer is performed by performing 8-byte transfer four times. Furthermore, if we divide the banks of cache memory 83 and 84 at the 5th bit from the bottom of the address, that is, at the 16-byte boundary, the block transfer data will be divided into cache memory 83 and 84 banks.
3 and cache memory 84 twice (16 bytes each)! You will be trapped.

On the other hand, when the instruction for write operation I is set in the request code register 20-10, the request address ( write address) is real address register 2 (1
-20 to real address registers 20-22, and read data from cache memory 83 or cache memory 84 is transferred to data registers 20-50. Further, information as to whether or not it is a cache hit is input to the decoder 20-11 and set in the request code register 20-12.

Thus, for write operations, request code registers 20-10. Real address register 20-2
Request code registers 20-12 from the first stage of 0
．． By moving the processing to the second stage of the real address registers 20-22 and leaving the first stage vacant, subsequent requests can be accepted. In other words, in a write operation, it is necessary to wait for the write data, so this kind of processing is possible.
Second stage request code register 20-12. Request code for write operation set in real address registers 20-22.

The requested address is the write data in the high-speed arithmetic circuit 50.
Wait for the write data to be prepared in the register,
A write operation is performed when write data is prepared.Although this is not a direct content of the present invention, in this embodiment, in the case of a cache hint, all data within the data width (e.g. 8 bytes) is written. Even if it is a partial write that does not rewrite the data, it is a full write that rewrites all the data within the data width, so that the processing speed particularly for writing to the main storage device 91 can be improved.

In other words, referring to address array 81 and cache
In a state where reading from the memory 83 or cache memory 84 is executed, the read data from the cache memory 83 or cache memory 84 is held in the data register 20-50 via the connection 207. When the write data is prepared, the write data transferred from the high-speed arithmetic circuit 5 through the connection 507 and the data register 2 of the address conversion control circuit 20 are transferred.
The cross bar switch 70 receives the pre-write data transferred from 0-50 through the selector 20-51 and the connection 207, and exchanges the data in byte units.
New write data is created. In other words, a write mask (8 bits if the data width is 8 bytes) is provided for each byte, and the mask is “1”.
” byte is replaced with pre-write data. In other words, byte with write mask 1 selects the write data of connection Fi07, and byte with write mask “0” selects the write data of connection 207. Select previous data. Note that this write mask is sent to the cross bar switch 70 through a connection 507 together with the write data, and after being received by the write mask receiving section 720, it is used to control the selector in the same way as the control signal through the connection 205. be done. By this operation, when a cache hit occurs, it is possible to perform a full write to the bus control circuit 30 and the main storage device 91 even for a write operation that is not a full write. In other words, full writing becomes possible. Note that in the case of a cache hit, the contents of data registers 20-50 are pre-write data, so the above processing is possible; however, in the case of a cache miss, the contents are undefined (only parity is guaranteed). ), full writing cannot be performed.In the case of such a cache miss, full writing is impossible.If it is a 2-byte write, it is directly sent to the bus control circuit 30 as a 2-byte partial write, Writing to cache memories 83 and 84 is also not executed.

Generally, the main storage device 91 has an error correction code (ECC) in units of 8 bytes, and reads 1 bit.

For example, when writing other than full 8-byte writing, such as partial 2-byte writing, after reading the corresponding 8-byte boundary data, only 2 bytes of the written data are corrected. It is necessary to replace the error correction code in 8-byte units and write it together with the data, which may result in a longer processing time compared to writing the whole thing, but in that case, the processing time will be delayed. In order to relieve
It is possible to shorten the processing time of the main memory device 91 by performing a full write operation on the main memory device 91.

Next, the operation of simultaneously transferring data between the LSI chip and the cache memory, which is another feature of the present invention, will be explained. In other words, in Figure 3, the request code
The register and real address register are in two stages, and the cache is divided into two banks.
Writing and reading can be performed simultaneously to the memories 83 and 84. Below, second stage request code register 20-12. Real address register 20-2
The operation will be described in the case where the write operation is set to 2 and the subsequent read operation is set to the request code register 20-10 and the real address register 20-20 of the first stage. In this case, the operation differs depending on the bank of the cache memory to which writing and reading are performed. Note that bank selection is performed according to the predetermined value of one bit in the request address, as described above.

+11 In the case of the same bank In this case, the second stage write operation takes priority, and one of the write addresses (contents of real address registers 20-22) is stored in DA address registers 20-40 or DA address registers 20-41. is set via the selector 20-23.20-42.20-43, a write address to the cache memory 83 or cache memory 84 is secured, and writing is performed.

Further, the first stage read operation is performed while waiting for the write operation to be completed.

(2) In the case of another bank In this case, for example, if writing is to bank #O (cache memory 83) and reading is to bank #l (cache memory 84), part of the write address is stored in the DA address registers 20-40. Part of the read address is AA
Address registers 20-30 and DA address registers 20-41. Therefore, in the second stage, the address of the cache memory 83 is secured by the DA address register 20-40, and the connection 507°20
7 creates write data, and at the same time the data is written to the cache memory 83 through connection 837, connection 3
07, the write data is sent to the bus control circuit 30 and written to the main memory device 91. In parallel, in the first stage, the AA address registers 20-30 and D
The addresses of the address array 81 and the cache memory 84 are secured by the address registers 20-41, and the data in the cache memory 84 is read through the connection 847. At this time, the subsequent destination is the instruction control circuit 10 or the arithmetic control circuit. The circuit 40 can return the above read data. However, since the high-speed arithmetic circuit 50 or the address conversion control circuit 20 is used for the second stage write operation, reading to these is not possible.

〔Effect of the invention〕

As explained above, in the arithmetic processing device of the present invention, the data path for reading and 8-input of the cache memory can be directly implemented using a chip having a cross bar switch function without using a bus method. Cache memory and LSI
Since it is connected to the chip, it is possible to minimize the total line length that forms the data path where data is transferred, which has the effect of realizing high-speed cache memory access. There is.

In addition, the cache memory is divided into two or more banks, and data can be transferred simultaneously to different LSI chips via a chip with a cross bar switch function.
This has the effect of greatly improving data transfer efficiency.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an information processing device including an arithmetic processing device of the present invention, FIG. 2 is an internal configuration diagram of the cross bar switch in FIG. 1, and FIG. 3 is an address conversion control circuit in FIG. 1. FIG. 2 is a diagram showing a part of the internal configuration of. In the figure, 90... Arithmetic processing unit, 91... Main storage device, 92... Input/output control device, 93... System control device, 94... System path, 10... Instruction control Circuit, 20...Address conversion control circuit, 30.
...Bus control circuit, 40...Arithmetic control circuit, 50...
- High-speed calculation circuit, 60... Control storage circuit, 70...
Cross bar switch, 81...Address array, 82...Copy address array, 83.84.
... Cache memory, 85... Control memory.

Claims (1)

[Scope of Claims] An arithmetic processing device comprising a cache memory and a plurality of LSI chips, in which data transfer is performed between the cache memory and two or more of the LSI chips, comprising: A cross bar that can divide the bank into two or more banks and connect any input/output terminals.
The cache is connected via a chip with a switch function.
A memory and two or more of the LSI chips are connected, and two or more different LSI chips and two or more different banks of the cache memory are connected via the chip having the cross bar switch function. An arithmetic processing unit characterized by simultaneously transferring data.