JPH01241920A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To reduce the pull-in time and to improve the stability by increasing a digital value of a phase difference adaptively when the digital numerical value representing the phase difference is at the outside of a predetermined range. CONSTITUTION:A shape difference between an inputted synchronizing signal SYNC and an internal synchronizing signal INTSYNC formed by a clock CK generated from the synchronizing signal SYNC is expressed by a digital numerical value (b), the digital numerical value (b) is integrated by an integration circuit 15, converted into a voltage by a D/A converter 16, the frequency of an oscillator 17 is controlled and phase-locked, then a phase difference detection circuit 13 decides whether or not the digital numerical value (b) is in a prescribed range. When the value is within the range, the digital numerical value (b) is outputted as it is and a gain adjustment circuit 14 increases adaptively the digital numerical when the value is within the range. Thus, the pull-in time at out of synchronization is reduced and the stability at the pull-in time is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a phase-locked loop circuit, and particularly relates to a phase-locked loop circuit, and in particular, when generating a pulse synchronized with an input synchronization signal, the synchronization pull-in time and the stability of the synchronization pull-in are improved. This invention relates to a phase-locked loop circuit with improved performance.

[Conventional technology]

A phase locked loop (PLL) circuit is a circuit that generates a pulse synchronized with an input synchronization signal.

Such a phase-locked loop circuit expresses the phase difference between the input synchronization signal and the internal synchronization signal generated based on the generated clock as a digital value, integrates the digital value, and converts it into a voltage to generate a control signal. The oscillator (VC
There is one in which the frequency of O) is controlled to synchronize the phase of the generated clock with the input synchronization signal.

This will be explained with reference to FIG. 2. FIG. 2 shows an example of this type of conventional phase-locked loop circuit, and this phase-locked loop circuit includes a phase comparison circuit 21, a phase difference counting circuit 22, , an integrating circuit 23 , a D/A converter 24 , a voltage controlled oscillator 25 , and a frequency dividing circuit 26 .

The synchronizing signal 5YNC is supplied to the phase comparison circuit 21, and the clock CK is taken out from the voltage controlled oscillator 25. The clock CK is also applied to the frequency divider circuit 26, from which an internal synchronizing signal INTSYNC is taken out as a frequency divided output, and this internal synchronizing signal NTSYNC is also applied as the other input of the phase comparator circuit 21.

Phase difference counting circuit 22, integrating circuit 23 and D/A converter 2
4 is provided between the above-mentioned phase comparator circuit 2I and the voltage controlled oscillator 25, which obtains a signal expressing the phase difference as a digit number, integrates this signal, and outputs the D/
The configuration is such that A-conversion is performed to form a control signal for controlling the oscillation frequency, and this is applied to the voltage controlled oscillator 25.

In this way, in the phase-locked loop circuit shown in Fig. 2,
The phase comparison circuit 2I compares the phase of the input synchronization signal 5YNC with the internal synchronization signal INTSYNC generated by the frequency dividing circuit 26 from the generated clock CK, and the phase difference is expressed as a digital value by the phase difference counting circuit 22. The integration circuit 23 integrates the signal, and the D/A converter 24 converts the voltage to control the frequency of the oscillator 25.
A pulse synchronized with C is generated.

[Problem to be solved by the invention]

However, in the case of a configuration in which this type of phase comparison output is digitized, integrated, and D/A converted to control the oscillation frequency, it has the following advantages. There is a problem with this aspect.

In other words, the conventional phase-locked loop circuit described above can create highly accurate and stable synchronization pulses by integrating the phase difference, but it is difficult to achieve synchronization due to large frequency deviations that occur when the power is turned on. The disadvantage is that it takes a considerable amount of time. Furthermore, if the accuracy of the integrating circuit 23 is made rough in order to shorten the synchronization pull-in time, there is a drawback that the oscillator 25 is directly affected by even subtle fluctuations, resulting in poor stability.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase-locked loop circuit that can shorten the pull-in time even when a large frequency shift occurs, such as when power is turned on, and can also avoid a decrease in stability.

[Means to solve the problem]

The present invention provides a phase gate loop circuit that obtains a signal that is phase-synchronized with an input synchronization signal, in which the phase of the synchronization signal is compared with an internal synchronization signal obtained from a clock generated based on the synchronization signal. a second means for expressing the phase difference obtained by the phase comparison as a digital value; a third means for determining whether the digital value is within a predetermined range; and a third means for determining whether the digital value is within a predetermined range; a fourth means capable of adaptively increasing the digital value; a fifth means for integrating the digital value of the fourth means; and a sixth means for converting the output of the fifth means into a voltage value. and a seventh means for controlling an oscillator according to the voltage value to generate the clock as an output; and an eighth means for dividing the clock from the seventh means and outputting the internal synchronization signal. It is characterized by having the following.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

As shown in FIG.
1, phase difference counting circuit 12, integrating circuit 15, and D/A
It includes a converter 16, a voltage controlled oscillator 17, a frequency dividing circuit 18, a phase difference detection circuit 13, and a gain adjustment circuit 14.

The other components except for the phase difference detection circuit 13 and the gain adjustment circuit 14 may be the same as those in FIG. 2.

That is, the phase comparator circuit 11 receives the synchronization signal 5YNC,
This circuit compares the phase with the internal synchronization signal INTSYNC obtained from the clock CK generated from the synchronization signal 5YNC, and the phase difference counting circuit 12 expresses the phase difference obtained by the above-mentioned phase comparison as a digital value. It is used as a means of outputting.

The clock CK is taken out as the output of the voltage controlled oscillator 17 whose oscillation frequency is controlled according to the supply control signal,
The internal synchronization signal rNTsYNc is obtained by frequency-dividing the clock CK by a frequency dividing circuit 1B.

Further, an integrating circuit 15 and a D/A converter 16 provided at the front stage of the voltage controlled oscillator 17 each integrate a digital value and convert the integrated output into a voltage value by D/A conversion. However, unlike the configuration shown in FIG. 2, the phase difference counting circuit 1
A gain adjustment circuit 14 is inserted between the gain adjustment circuit 2 and the integration circuit 15, and a phase difference detection circuit 13 for controlling the gain adjustment circuit 14 is also provided.

The output of the phase difference counting circuit 12 is applied to the phase difference detection circuit 13 . The phase difference detection circuit 13 is a circuit that determines whether the digital value obtained by the phase difference counting circuit 12 is within a predetermined range, and the gain adjustment circuit 14 is controlled according to the determination result. . The gain adjustment circuit 14 constitutes a means for adaptively increasing the digital value according to the determination result, and the digital value is transmitted to the integration circuit 15 via the gain adjustment circuit 14.
given to.

Specifically, when the phase difference detection circuit 13 detects that the digital value is within a predetermined range, the digital value is output as is, and when it is outside the range, the digital value of the phase difference is output. Output by increasing the size adaptively.

In this embodiment, in the circuit that generates the signal phase-synchronized with the input synchronization signal, the synchronization signal 5Y
A phase comparison circuit 11 that compares the phases of the NC and an internal synchronization signal INTSYNC generated from the clock CK generated from the synchronization signal 5YNC, and a phase difference counting circuit 12 that serves as a means for expressing the phase difference resulting from the phase comparison as a digital value. , a phase difference detection circuit 13 as a means for determining whether the digital value is within a predetermined range, and a gain adjustment circuit 14 as a means for adaptively increasing the digital value based on the determination. , an integration circuit 15 that integrates this adaptively increased digital value, and a D/A that converts the value resulting from the integration into a voltage.
A converter 16, a voltage controlled oscillator 17 constituting a means for controlling an oscillator with the voltage value obtained by the voltage conversion, and a voltage controlled oscillator 17 that divides the clock CK generated by the oscillator to generate the internal synchronization signal I.
It has a frequency divider circuit 18 that generates NTSYNC.

Next, the operation of the circuit of this embodiment will be explained.

The phase comparison circuit 11 receives the input synchronization signal 5YNC,
The phase difference a between the clock CK generated from the synchronization signal 5YNC and the internal synchronization signal INTSYNC generated by the frequency dividing circuit 18 is output. The phase difference counting circuit 12 already expresses the phase difference a as a digital value using the edge of the synchronizing signal 5YNC as a reference. A digital value is inputted to the phase difference detection circuit 13, and the phase difference detection circuit 13 detects whether the digital value is within a predetermined range and outputs a detection signal C.

Here, if it is outside the predetermined range,
In response to the detection signal C, the gain adjustment circuit 14 outputs a numerical value d, which is an adaptively increased value of the input digital numerical value s. In such a case, the integrating circuit 15 integrates the adaptively increased numerical value d and outputs an integral value e. Then, the D/A converter 16 converts the integral value e into a DC voltage value f, and the voltage controlled oscillator 17 outputs a clock CK whose frequency is controlled by the DC voltage value f.

On the other hand, if the result of the determination by the phase difference detection circuit 13 is within a predetermined range, the gain adjustment circuit 14 outputs the input as is, and this is given to the integration circuit 15. D/A conversion is performed and the oscillation frequency is controlled.

In this way, the phase-locked loop circuit expresses the phase difference between the input synchronizing signal 5YNC and the internal synchronizing signal INTSYNC generated from the clock CK generated from the synchronizing signal 5YNC as a digital value, and integrates this digital value. A circuit for controlling the frequency of an oscillator and phase synchronizing the frequency of the oscillator by converting the voltage, means for determining whether the digital value is within a predetermined range and outputting a signal; If the digital value of the phase difference is within the range, the digital value of the phase difference is output as is, and if it is outside the range, the digital value of the phase difference is adaptively increased. Synchronization pull-in time and stability can be improved without any loss.

In other words, even when there is a large frequency shift that occurs when the power is turned on, synchronization does not take a considerable amount of time unlike conventional methods, and synchronization can be achieved quickly. It is also possible to avoid a decrease in stability that would occur if the surface was made coarser.

〔Effect of the invention〕

As explained above, according to the present invention, the phase difference between the input synchronization signal and the internal synchronization signal generated from the clock generated from the synchronization signal is expressed as a digital value,
When integrating this digital value and converting it into voltage to control the frequency of the oscillator and synchronize the phase, it is determined whether the digital value is within a predetermined range, and if it is within the range, the digital value is Since it is possible to output the digital value as is and to increase the digital value adaptively when it is outside the range, it is possible to shorten the acquisition time when the synchronization is lost and improve the stability when the synchronization is acquired.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the phase-locked loop circuit of the present invention, and FIG. 2 is a block diagram showing a conventional phase-locked loop circuit. 11... Phase comparison circuit 12... Phase difference counting circuit 13... Phase difference detection circuit 14... Gain adjustment circuit 15... Integrating circuit 16... ...D/A converter 17...Voltage controlled oscillator 18...Frequency divider circuit 5YNC...Input synchronization signal INTSYNC...Internal synchronization signal CK...Clock a... ...Phase difference b...Digital value (phase difference expressed as a digital value) C...Detection signal d...Digital value (phase difference of digital value that is adaptively increased) e ...Integral value f...DC voltage value Agent Yoshiyuki Iwasa, patent attorney

Claims (1)

[Claims] (1) In a phase-locked loop circuit that obtains a signal that is phase-locked to an input synchronization signal, a first circuit that performs a phase comparison between the synchronization signal and an internal synchronization signal obtained from a clock generated based on the synchronization signal. a second means for expressing the phase difference obtained by the phase comparison as a digital value; a third means for determining whether the digital value is within a predetermined range; a fourth means capable of adaptively increasing the numerical value; a fifth means for integrating the digital numerical value of the fourth means; and a sixth means for converting the output of the fifth means into a voltage value. , a seventh means for controlling an oscillator according to the voltage value and generating the clock as an output; and an eighth means for dividing the clock from the seventh means and outputting the internal synchronization signal. A phase-locked loop circuit comprising: