JPH012420A - data transfer circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data transfer circuit for causing a data processing device to read changing digital data such as switch operation data on an operation panel in another part. It is.

[Conventional technology]

FIG. 5 is a block diagram showing a conventional data transfer circuit. In the figure, 1 is an operation panel, 2 is a control section, 3 is an initial reset signal that initializes the circuit, and 4 is a series of switches that start transferring data. data transfer start signal, 5
is data transfer timing, 6 is a timing generation circuit that generates initial reset signal 3, data transfer start signal 4, and data transfer timing 5, 7 is a switch, 8 is parallel data from switch 7, 9 is data transfer of parallel data 8 This is a parallel-serial shift register (hereinafter referred to as PS shift register) that reads data at start signal 4 and converts it to serial data at data transfer timing 5. The operation panel 1 is composed of a switch 7 and a PS shift register 9.

Further, 10 is serial data output from the PS shift register 9 and sent to the control unit 2, and 11 is a serial-parallel shift register (hereinafter referred to as SP shift register) that inputs the serial data 10 and converts it into parallel data at data transfer timing 5. ), 12 is a data register that temporarily holds the parallel data of the SP shift register 11 using the data transmission start signal 4, 13 is a gate signal for outputting the data of the data register 12, and 14 is the ht
A data processing device 15 outputs the gate signal 13, reads the parallel data 14, and processes it in software according to a program.

fill Part 8 2 is the timing source v! It is composed of an I6, an SP shift register 11, a data register 12, and a data processing device 5.

Further, FIG. 6 shows a flowchart of a program executed when the data processing device 15 reads the parallel data 14 in the conventional circuit configuration shown in FIG.

In this FIG. 6, step ST1 is a comparison process of reading new parallel data 14 and comparing it with the previously read old data, and step ST2 is a comparison process of checking whether the new data and old data are different as a result of the comparison process. Step ST3 is an execution process that the data processing device 15 should take if the new data and old data are different. Step ST4 is a data update process that replaces old data with new data. be.

Next, the operation will be explained. When the switch data transfer circuit starts operating, first, the initial reset signal 3 is sent from the timing and generation circuit to the PS shift register 9, S
It is output to the P shift register 11 and the f-data register 12, and these are set to the v'J period.
The start ji number 4 is output to the PS shift register 9 and the data register 12, and this data transfer start signal 4 causes the PS
Switch T or Rano parallel data 8 is 1 in shift register 9
On the other hand, the data register 12 reads the data of the SP shift register 11, but immediately after the initial reset signal 3 is output, the SP shift register 11 remains initialized and the serial data 10 has not yet been input manually. Therefore, the data contents are initial values.

The ARM outputs data transfer timing 5, and at this data transfer timing 5, the PS shift register 9 transfers the parallel data 8 read earlier from the switch 7 one by one.
The real data 10 and the L''C8P shift register 11 are outputted, and the SP shift register 11 inputs the serial data 10 one by one, converts this serial data into parallel data, and outputs it to the data register 12.

After all of the parallel data 8 have been transferred from the PS shift register 9 to the SP shift register 11, the data transfer start signal 4 is output again from the timing generation circuit 6, and each section repeats the above operations.

The data register 12 updates its contents every time the data transfer start signal 4 is output, while the data processing device 15 outputs the gate signal 13 and outputs the parallel data 1 from the data register 12.
4 and performs the processing shown in FIG. 6 according to the software program.

In this FIG. 6, in step ST1, the parallel data 14 newly output from the data register 12 is read,
It is compared with the previously read old data, and the result of this comparison process is determined in step SP2 whether or not the new data and old data are different. If they are not different, there is no need to do anything and the process ends. let

If the new data and old data are different as a result of the determination in step ST2, the process proceeds to step ST3.

In the execution process of this step ST3, different data, that is, the action according to the operation of the switch T, is performed, and in step ST4, a data update process is performed to replace the old data with new data, and the new data is retained for the next processing cycle. and ends the process.

[Problem that the invention seeks to solve]

Since the conventional switch data transfer circuit is configured as described above, it is necessary to compare the data with the previous data every time new data is transferred by the data processing device 15, and there is no difference in the data as a result of the comparison. Even without it, step S
There was a problem in that it took a long time to perform the comparison process each time at T1.

This invention was made to solve the above-mentioned problems, and it is a data transfer method that eliminates the need for the data processing device to compare new data with old data every time, and shortens the program processing time of the data processing device. The purpose is to obtain a circuit.

[Means for solving problems]

The data transfer circuit according to the present invention converts changing parallel data on the data sending side into serial data using a parallel-serial shift register, and shifts the data by the number of data to be converted into serial data using a first shift register. , a mismatch between the serial data of this first shift register and the parallel-serial shift register is detected by an exclusive OR gate, and the output of this exclusive OR gate or the output of the parallel-serial shift register is received on the receiving side. Then, the detection and holding circuit on the receiving side detects and holds the mismatch bit (D) on the output data of the exclusive OR gate, and when the number of mismatch bits is detected, an interrupt is generated to the data processing device, and the data held in the data register is is read into a data processing device and processed.

[Effect]

The first sister register and the exclusive OR gate in this invention transmit the data as serial data while checking each change in data, and the detection and holding circuit on the receiving side detects whether or not there is a "mismatch" bit in the serial data. Detects only
Only when this is detected, an interrupt is issued to the data processing device, and the data processing device receives the data on the receiving side, converts the serial data into parallel data, reads the data, and processes it.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, when explaining the configuration, parts that are the same as those in Figure 5 are given the same reference numerals to avoid redundant explanation, and in order to make the differences with Figure 5 clear, parts that are different from Figure 5 will be highlighted. I will explain.

In FIG. 1, 13 is a gate signal for outputting data from the data register 12, and 14 is a gate signal 1.
Parallel data of the next data register 12 read at 3, 1
5 is a data processing device that outputs the gate signal 13, reads the parallel data 14, and processes it in software according to a program; 20 inputs the serial data from the PS shift register 9 and shifts it by the number n of parallel data 8; The first shift register (hereinafter referred to as S shift register) that outputs the output, 21 is an exclusive OR gate (hereinafter referred to as E
(referred to as an XOR gate), 22 is the serial data 10
JK flip 70 tube circuit (hereinafter referred to as JKFF) that detects the presence or absence of the "mismatch" bit, 23 is JKFF22
A D-type flip-flop circuit (hereinafter referred to as DFF) reads the detection result at the next data transfer start timing after the transfer of a series of serial data 10 is completed, and if there is a "mismatch" bit, interrupts the data processing device 15.
, 24 are logical sum gates (hereinafter referred to as OR gates), and the other configurations are the same as in FIG.

2(a) shows the data transfer start signal 4, FIG. 2(b) shows the data transfer timing 5, and FIG. 2(e) shows the serial data 10.

FIG. 3 shows the data processing device 15 in the circuit configuration shown in FIG.
3 shows a flowchart of a program executed when reading parallel data 14. In FIG. 3, step ST1
1 determines whether there is an interrupt from the DFF23,
Step ST12 is a judgment process that determines subsequent processing, and step ST12 is a change data detection process in which new parallel data 14t is read and which data has a "mismatch j, that is, a change."
The execution process to be taken by step ST14 is to convert the original data held by the data processing device 15 into parallel data 14.
This is a data update process in which data is updated in response to "unmatched" data, that is, changes.

Next, the operation will be explained. When the switch data transfer circuit shown in FIG. 1 starts operating, first the initial reset signal 3 is output from the timing generation circuit 6, and the PS shift register 9, S shift register 20, SP shift register 11, data register 12, and DFF 23 are output. is reset.

After that, the data transfer start signal 4 shown in FIG.
The signals are sent to the shift register 11, respectively.

As a result, the parallel data 8 from the switch 7 is read into the PS shift register 9, while the data from the SP shift register 11 is read into the data register 12.

Subsequently, data transfer timing 5 shown in FIG. 2 is sent from the timing generation circuit 6 to the PS shift register 9, S shift register 20, JKFF 22, DFF 23, and SP shift register 11, respectively.

At this data transfer timing 5, i) S shift register 9
outputs the previously read parallel data 8 to the EXOR gate 21 and the S shift register 20 one by one.

Since the S shift register 20 is reset by the initial reset signal 3, the serial data 10 shown in FIG. The data in the PS shift register 9 becomes the same, and when this data transfer cycle ends, the SP shift register 11 has the same contents as the PS shift register 9.

At this time, if the parallel data 8 is being manipulated, "unmatched" data will appear in the serial data 10!
7, JKFF22 is set.

With the next data transfer start signal 4, the data register 12 is set to SP.
Read the data of shift register 11, DF'F23
reads the “mismatch” bit detection result of the JKFF 22 and issues an interrupt to the data processing device 15.

At this time, the JKFF 22 needs to be reset for the next data transfer cycle, so the data transfer start timing is input to this terminal, and the final bit of the serial data 10 is set to an invalid level.

The data processing device 15 1) When there is an interrupt from the FF 23, it outputs a gate signal to the data register 12 and reads the parallel data 14 output from the data register 12.

Furthermore, the gate signal 13 is passed through the OR gate 24 to the DFF
23 and eliminates the interrupt.

The flowchart of the program for reading the parallel data 14 from the data register 12 of the data processing device 15 at this time is as shown in FIG.

In FIG. 3, in step 5T11, it is determined whether or not there is an interrupt from the DFF 23, and if the result of the determination is that there is no interrupt, the process ends without doing anything.

If there is an interrupt in step ST11, the gate signal 1 is sent from the data processing device 15 in step 5112.
3 is output to the data register 12, new parallel data 14 output from the data register 12 is read, and data detection processing is performed to detect "unmatched" data, that is, change data.

Next, in step ST13, necessary measures are taken corresponding to the changed data, and finally, in step ST14, in order to grasp the state of the switch T, the bit corresponding to the changed data of the original data held from before is inverted. Then, the series of processing ends.

In addition, in the above embodiment, the S shift register 20, gXO
The R gate 21 is placed on the operation panel 1, and the "mismatch" data is set as serial data 10. However, as shown in FIG. may be converted into serial data 10 in the PsS shift register 9, and this serial data 10 may be transmitted as is as serial data 10. In this case, the processing performed by the data processing device 15 may be the same as that in FIG. 3 of the above embodiment, A similar effect can be obtained.

Further, in FIG. 4, the "mismatch" serial data from the EXOR gate 21 is input to the SP shift register 11, but the serial data 10 may be input instead. At this time, the processes performed by the data processing device 15 include the detection method of the change data detection process of step ST12 in FIG. 3, and the data update process of step 5T14, respectively.
The comparison process in step ST1 and the data update process in step ST4 in the figure are the same, but the effect obtained is the first.
It is the same as the embodiment shown in the figure.

Furthermore, in the embodiment shown in FIG. 1 above, the case of transferring switch data was explained, but as long as it is digital data that changes, position information such as track poles etc. may also be used.
The same effects as in the above embodiment are achieved.

〔Effect of the invention〕

As described above, according to the present invention, the PS
By using an EXOR gate to detect a mismatch between the output serial data of the shift register and the output serial data of the S shift register, data changes are detected at the same time as data transfer, and only when a mismatch occurs, the data processing device is instructed to process new data. Since the data processing apparatus is configured to perform this, there is no need for the data processing device to read new data unnecessarily and compare it with old data, which has the effect of shortening the program processing time.

[Brief explanation of the drawing]

Fig. WJ1 is a block diagram showing a data transfer circuit according to an embodiment of the present invention, Fig. 2 is a signal timing chart for explaining the operation of the above embodiment, and Fig. 3 is a program of the data processing device in the above embodiment. 4 is a block diagram showing a data transfer circuit according to another embodiment of the present invention, FIG. 5 is a block diagram showing a conventional data transfer circuit, and FIG. 6 is a block diagram showing data processing in the conventional data transfer circuit. A flowchart showing a program of the device, a register, 11 an SP shift register, 12 a data register, 15 a data processing device, 20 an S shift register, 21 an EXOR gate, and 25 an ejection holding circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant: San-ai Electric Co., Ltd. (2 others)

Claims (1)

[Claims] A parallel-to-serial shift register that reads changing parallel digital data on the data sending side and converts it to serial data; and a parallel-to-serial shift register that reads serial data from this parallel-to-serial shift register and shifts it by the number of data read by the parallel-to-serial shift register. a first shift register; an exclusive OR gate that detects a mismatch between the serial data from the parallel-serial shift register and the serial data from the first shift register; and data output from the exclusive OR gate. a detection and holding circuit on the receiving side that detects the above mismatched bit and temporarily holds the result, and inputs the output data of the parallel-serial shift register or the output data of the exclusive OR gate and converts it into parallel data. A serial-parallel shift register, a data register that temporarily holds the parallel data converted by the serial-parallel shift register, and the exclusive OR gate generate an interrupt at the output of the detection and holding circuit only when the exclusive OR gate detects the mismatch. and a data processing device that takes in and processes parallel data that has been applied and is held in the data register.