JPH01243620A - Digital phase locked loop oscillator - Google Patents

Abstract

PURPOSE:To widen the pull-in range of a frequency compared to a conventional one even if the frequency-division rate of a reversible counter for suppressing a jitter is increased by adding and connecting a frequency control part between the reversible counter and a variable frequency-divider. CONSTITUTION:When the phase delay of an output signal continuously occurs, for example, the counting result of the reversible counter 11 is reduced in the frequency control part 6 and the frequency-division rate of the frequency divider 13 is correspondingly reduced. Consequently, the frequency of the phase forward shift of the output signal is increased, and it follows the phase of the input signal. When the phase of the output signal is in a locked state, the counting result of the reversible counter 11 holds a value at the time of locking for a prescribed period, whereby the frequency of the output signal is held to the value at the time of locking for the prescribed period. A mobile frequency follows the value at the time of locking so as to be changed. The pull-in range of the frequency is prevented from coming narrow even if the frequency-division rate of the counter 2 for suppressing the jitter is increased.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a digital phase-locked oscillator.

[Conventional technology]

A conventional digital phase synchronized oscillator has a configuration as shown in the block diagram of FIG. That is, the main oscillator 3,
The phase comparator 1 detects the phase error between the output signal of the digitally controlled oscillator consisting of the variable frequency divider 4 and the frequency divider 5 and the input signal, and determines whether the phase of the output signal lags or leads. A signal indicating this is sent to the reversible counter 2. The reversible counter 2 counts up (or counts down) a signal indicating phase lag (or phase lead), and
Every time the count result reaches 10M (or -M, where M is a preset natural number), a pulse of a delay signal (or advance signal) is sent out and the count result is reset. The variable splitter 4 uses a frequency division ratio of N when pulses of a delayed signal and a leading signal do not arrive, a frequency division ratio of (N-1) when a pulse of a delayed signal arrives, and a frequency division ratio of (N-1) when a pulse of a leading signal arrives. The 0 divider 5 divides the clock signal sent from the main oscillator 3 and sends it to the divider 5. The divider 5 further divides the divided clock signal sent from the variable divider 4 by a frequency division ratio P.
Divide the frequency by and output.

In this phase-locked oscillator, if there is a phase lag in the output signal over M periods, for example, the output signal is given a phase forward shift of one period of the clock signal sent from the main oscillator 3,
Follows the input signal phase.

[Problem to be solved by the invention]

In the conventional digital phase synchronized oscillator described above, the frequency pull-in range Δf is determined by the following equation (1).

Δf o = f o / (M-N-P)
(1) Therefore, if the frequency division ratio M of the reversible counter 2 is increased for the purpose of suppressing the influence of jitter on the input signal, there is a problem that the frequency pull-in range becomes narrower.

In particular, if the output frequency accuracy of the main oscillator 3 is not sufficiently high, there is a high possibility that the pull-in will not be possible, and the above-mentioned problem is significant.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital phase synchronized oscillator that solves the above-mentioned problems and allows a wider frequency pull-in range than before even if the frequency division ratio of a reversible counter for jitter suppression is increased.

[Means to solve the problem]

The digital phase synchronized oscillator of the present invention includes a phase comparator that detects a phase error of an output signal with respect to an input signal, and a frequency of occurrence of lead and lag of the phase error in both positive and negative directions in response to the detection result of the phase comparator. a reversible counter that counts and frequency-divides and sends a signal instructing backward shift and forward shift of the output signal phase; The occurrence frequency of one of the backward shift and the forward shift in its own sending signal is varied in response to a signal obtained by counting the shift occurrence frequency in both positive and negative directions and further counting the frequency division result in both positive and negative directions. a frequency control section to be set, and a frequency division ratio variably set in response to the logical sum signal of both transmission ratio signals of the reversible counter and the frequency control section, and giving the backward shift and the forward shift to the output signal phase. and a digitally controlled oscillator that has a variable frequency divider and divides the clock signal sent out from the main oscillator and sends it out as the output signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram of a boot 2 showing an embodiment of the present invention. The phase synchronized oscillator shown in the figure has a configuration in which a frequency control section 6 is additionally connected between the reversible counter 2 and the variable branching unit 40 in the conventional configuration shown in FIG. The reversible counter 2 counts up and down the output signal of the phase comparator 1, which detects the phase error between the input signal and the output signal, at a predetermined frequency division ratio, and the lead and lag signals obtained by the reversible counter 2 are passed through the OR gate 7, respectively.
and sent to the 80 input terminal. Both transmission ratio signals of the OR gates 7 and 8 are given to the variable splitter 4 and the frequency control section 6. The reversible counter 10 of the frequency control section 6 counts up the pulses sent out from the OR gate 7 and counts down the pulses sent out from the OR gate 8, and each time the absolute value of the count result reaches a predetermined number, A pulse indicating this timing and a pulse indicating whether the sign of the count result is positive or negative are sent out to reset the count result.

In response, the reversible counter 11 counts the pulses sent out by the reversible counter 10 in the direction indicated by the sign, and provides a signal indicating the count result to the branching unit 13. Frequency divider 1
3 has a variable frequency division ratio, and when the count result of the reversible counter 110 increases (or decreases), the frequency division ratio increases (or decreases). On the other hand, the frequency divider 14 has a preset and fixed frequency division ratio, and together with the frequency divider 13, further divides the frequency of the clock signal sent out by the main oscillator 3 by the frequency divider 12. The output signal of the frequency divider 13 is sent to the OR gate 8,
Further, the output signals of the frequency divider 14 are sent to the OR gates 7, respectively. The variable divider 4 uses a frequency division ratio of N when a pulse does not arrive from either OR gate 7 or 8, and a frequency division ratio of (N+1) (or () when a pulse arrives from OR gate 7 (or 8). N-1)) divides the frequency of the output clock signal of the main oscillator 3 and sends it to the divider 5 to generate an output signal.

In this embodiment, for example, if the phase delay of the output signal continues to occur, the count result of the reversible counter 11 decreases, and the frequency division ratio of the divider 13 decreases accordingly. As a result, the frequency at which the variable division divider 4 reaches the frequency division ratio (N-1) increases, so the frequency at which the phase of the output signal is shifted forward also increases to follow the input signal phase. In the conventional case, when the output signal phase is shifted, the frequency of the output signal becomes lower than that of the main oscillator 3.
In contrast, in this embodiment, the count result of the reversible counter 11 retains the value at the time of locking for a while, so the frequency of the output signal remains unchanged for a while. Retains the value at the time of period lock. In other words, whereas the free-running frequency in the conventional case is determined by the N-divided value of the clock frequency, the free-running frequency in this embodiment can be varied to follow the value at the time of lock, so that jitter suppression can be improved. Therefore, even if the frequency division ratio of the reversible counter 2 is increased, the frequency pull-in range does not become narrower.

〔Effect of the invention〕

As explained above, the present invention has the effect of realizing a digital phase synchronized oscillator that can have a wider frequency pull-in range than the conventional one even if the frequency division ratio of the reversible counter for jitter suppression is increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional digital synchronous oscillator. 1... Phase comparator, 2, 10, 11...
・Reversible counter, 3... Main oscillator, 4...
...Variable divider, 5.12-14... Frequency divider,
6... Frequency control section, 7.8... Logical sum gate. Agent Patent attorney Uchihara Construction (times

Claims (1)

[Claims] a phase comparator that detects a phase error of an output signal with respect to an input signal; and in response to the detection result of the phase comparator, the frequency of occurrence of the advance and lag of the phase error is counted in both positive and negative directions, and the frequency is divided and outputted. A reversible counter that sends a signal instructing a backward shift and a forward shift of a signal phase, and counts the frequency of occurrence of the backward shift and the forward shift in both positive and negative directions using a logical sum signal of both the reversible counter and its own sending signals. a frequency control unit that variably sets the frequency of occurrence of one of the backward shift and the forward shift in its own sending signal in response to a signal obtained by further counting the frequency-divided result in both positive and negative directions, and the reversible counter; and a variable frequency divider that variably sets a frequency division ratio in response to the OR signal of both output signals of the frequency control section and provides the backward shift and the forward shift to the output signal phase, and outputs the main oscillator. A digital phase synchronized oscillator comprising: a digitally controlled oscillator that frequency-divides a clock signal and sends it out as the output signal.